A IC device manufacturing method includes: forming first through sixth active areas; forming first through fourth gate structures, wherein: the first through fourth gate structures have a same length, and each of the first through fourth gate structures has a first end, a second end opposite to the first end, and is continuously conductive from the first to second end; forming a first isolation structure abutting first ends of the first and second gate structures; forming a second isolation structure abutting second ends of the first and second gate structures; and forming a third isolation structure abutting first ends of the third and fourth gate structures, wherein: the third isolation structure is between the first and second isolation structures, the third isolation structure is spaced from the first isolation structure by a first distance, and the third isolation structure is spaced from the second isolation structure by the first distance.

A high-speed multi-write read only memory array includes word lines, select lines, bit lines, and sub-memory arrays. There are a first word line, a first select line, a second select line, a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array includes a first memory cell coupled to the first word line, the first select line, and the first bit line, a second memory cell coupled to the first word line, the first select line, and the second bit line, a third memory cell coupled to the first word line, the second select line, and the third bit line, and a fourth memory cell coupled to the first word line, the second select line, and the fourth bit line.

A semiconductor device includes a substrate including an active area and a well region, a bitcell including a first gate structure and a second gate structure extending in a first direction across the active area and spaced apart in a second direction; a first conductive structure at a first side of the first gate structure; a second conductive structure between a second side of the first gate structure and a first side of the second gate structure; and a third conductive structure at a second side of the second gate structure; a fourth conductive structure vertically overlapping the well region; a first conductor connected to the first conductive structure and the third conductive structure; a second conductor connected to the fourth conductive structure; and a third conductor connected to the first and second gate structures. The second and fourth conductive structures are electrically connected to the well region.