The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.

A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.

A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.

A semiconductor device with an air gap includes a plurality of gate stacks disposed on a substrate; a liner layer conformally covering the gate stacks and the substrate; and a dielectric stack disposed on the liner layer on the gate stacks. The air gap is formed between the liner layer and the dielectric stack on two adjacent gate stacks. A height of the air gap is greater than heights of the two adjacent gate stacks, and the air gap includes: a lower portion between the two adjacent gate stacks, sidewalls and a bottom of the lower portion exposing the liner layer; a middle portion above the lower portion; and an upper portion above the middle portion. Sidewalls of the upper portion expose the dielectric stack, a top surface of the upper portion is covered by the dielectric stack, and the upper portion has a smaller width than the lower portion.

The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.

The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.

An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.