A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.

The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a top selective gate cut and two structure strengthen plugs in an upper portion of the alternating dielectric stack, wherein each structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a plurality of channel structures in the alternating dielectric stack; forming a plurality of gate line silts in the alternating dielectric stack, wherein each gate line slit exposes a sidewall of one enlarged connecting portion of a corresponding structure strengthen plug; transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug.

A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate layer, the gate dielectric layer, the charge storage layer using the patterned metal gate layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.

A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.

A memory device includes a cell wafer including a memory cell array; a first logic wafer bonded to one surface of the cell wafer, and including a first logic circuit which controls the memory cell array; and a second logic wafer bonded to the other surface of the cell wafer which faces away from the one surface, and including a second logic circuit which controls the memory cell array.

A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.