A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.

A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.

A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.

A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.