A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.

Provided is a non-volatile memory including a conductor layer, a memory device, and a selector. The selector is located between and electrically connected to the memory device and the conductive layer. The selector includes a metal filling layer, a barrier layer, and a rectify layer. The metal filling layer is electrically connected to the memory device. The barrier layer is located on the sidewall and the bottom surface of the metal filling layer. The rectify layer is wrapped around the barrier layer. The rectify layer includes a first portion and a second portion. The first portion is located between the barrier layer on the bottom surface of the metal filling layer and the conductive layer. The second portion and the metal filling layer sandwich the barrier layer on the sidewall of the metal filling layer. The first portion has more diffusion paths of metal ions than the second portion.

A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.

A semiconductor device includes a single poly non-volatile memory device including a sensing and selection gate structure, an erase gate structure, and a control gate structure. The sensing and selection gate structure includes a sensing gate and a selection gate, a bit line, a word line disposed on the selection gate, and a tunneling gate line. The erase gate structure includes an erase gate, and an erase gate line disposed near the erase gate. The control gate structure includes a control gate disposed on the substrate, and a control gate line disposed near the control gate. The sensing gate, the selection gate, the erase gate and the control gate are connected by one conductive layer. The erase gate structure implements a PMOS capacitor, an NMOS transistor, or a PMOS transistor. The semiconductor device includes a single poly non-volatile memory device including a separate program area and erase area.

A semiconductor device includes a single poly non-volatile memory device including a sensing and selection gate structure, an erase gate structure, and a control gate structure. The sensing and selection gate structure includes a sensing gate and a selection gate, a bit line, a word line disposed on the selection gate, and a tunneling gate line. The erase gate structure includes an erase gate, and an erase gate line disposed near the erase gate. The control gate structure includes a control gate disposed on the substrate, and a control gate line disposed near the control gate. The sensing gate, the selection gate, the erase gate and the control gate are connected by one conductive layer. The erase gate structure implements a PMOS capacitor, an NMOS transistor, or a PMOS transistor. The semiconductor device includes a single poly non-volatile memory device including a separate program area and erase area.

A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.

A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.