A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate PMOS transistor area, P-type impurities implanted into the logic gate in the select gate PMOS transistor area are diffused into an N-type floating gate polysilicon layer to convert the N-type floating gate into a P-type floating gate by a subsequent high temperature heating process, so that it is possible to successfully form a select gate PMOS transistor having a small surface channel threshold value in a 55 nm process flash memory unit, and achieve mass production. Further, a two-step growth process of the logic gate and a process for separating the logic gate can form a surface channel of the select gate PMOS transistor having a smaller threshold value without affecting the floating gate doping of the control gate PMOS transistor.

Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.

A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate PMOS transistor area, P-type impurities implanted into the logic gate in the select gate PMOS transistor area are diffused into an N-type floating gate polysilicon layer to convert the N-type floating gate into a P-type floating gate by a subsequent high temperature heating process, so that it is possible to successfully form a select gate PMOS transistor having a small surface channel threshold value in a 55 nm process flash memory unit, and achieve mass production. Further, a two-step growth process of the logic gate and a process for separating the logic gate can form a surface channel of the select gate PMOS transistor having a smaller threshold value without affecting the floating gate doping of the control gate PMOS transistor.

A semiconductor device that can be downsized more than ever before is provided. A semiconductor device 10 includes: an insulating layer 21 provided on an upper side of a substrate 20; a conductor 110 provided within the insulating layer 21; a conductor 120 provided within the insulating layer 21 and facing the conductor 110 in a first direction parallel with a surface of the substrate 20; and an insulating film 130 provided between the conductor 110 and the conductor 120. A thickness of the insulating film 130 in the first direction is smaller than both of a thickness of the conductor 110 in the first direction and a thickness of the conductor 120 in the first direction. A relative permittivity of the insulating film 130 is higher than a relative permittivity of the insulating layer 21. The conductor 110 and the conductor 120 extend in a second direction intersecting the first direction and parallel with the substrate 20.