A driving substrate includes a base material, a plurality of active devices, a thermal-conducting pattern layer and a buffer layer. The active devices are separately arranged on the base material. Each active device includes a gate, a channel layer, a gate insulation layer, a source and a drain. The source and the drain expose a portion of the channel layer to define a channel region. The thermal-conducting pattern layer is disposed on the substrate and includes at least one thermal-conducting body and at least one thermal-conducting pattern connected to the thermal-conducting body. The thermal-conducting pattern corresponds to a location of at least one of the channel region, the channel layer, the gate, the source and the drain and each active device. The buffer layer is disposed on the substrate and covers the thermal-conducting pattern layer, and is located between the thermal-conducting pattern and each active device.

Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.

A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

A display panel includes a first substrate, an upper capacitor electrode, a capacitor dielectric layer, a second substrate opposite to the first substrate, a conductive bump, an electroluminescent layer, and a counter electrode. The upper capacitor electrode is disposed on an inner surface of the second substrate. The upper capacitor electrode is disposed on an inner surface of the second substrate. The capacitor dielectric layer covers the upper capacitor electrode of the second substrate. The first substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The conductive bump is protrusively disposed on the first capacitor electrode of the first substrate. The electroluminescent layer is sandwiched between the pixel electrode and the counter electrode.

An electronic or optoelectronic device includes: (1) a semiconductor layer; (2) a dielectric layer in contact with the semiconductor layer and including a polar elastomer; and (3) an electrode. The dielectric layer is disposed between the electrode and the semiconductor layer, and the polar elastomer includes a backbone structure and polar groups that are bonded as side chains to the backbone structure, and each of the polar groups includes 2 or more atoms.

A synaptic transistor based on a metal nano-sheet and a method thereof are provided. A self-assembled floating gate layer is formed. The floating gate layer prevents leakage of electric charges transmitted from a channel layer, and also temporarily stores the transmitted electric charge. Thus, the synaptic transistor may be used as an effective memory for storing.

Devices, materials and methods for producing and integrating carbon nanotubes (CNT) into TFTs to form unipolar CNT TFTs are provided. CNT TFTs comprise doped layers between the CNT active layer and the source/drain electrodes capable of providing a carrier-trapping function such that unwanted carrier charge injection is suppressed between the electrodes allowing for the unipolar operation of CNT TFTs. Methods and apparatus for forming unipolar N- or P-type SWCNT TFTs are also provided.