Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

A thin film transistor array including a substrate, thin film transistors each including a gate electrode formed on the substrate, a source electrode, a drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, an interlayer insulation film formed on the drain electrode, and an upper pixel electrode formed on the interlayer insulation film, and an insulation layer having light shielding property is formed between adjacent upper pixel electrodes.

A thread-based transistor includes a channel thread, a gate wire, and an ion gel. The channel thread includes a textile core that includes a source segment, a drain segment, and a gap segment that is between the source segment and the drain segment. Both the source segment and the drain segment are coated by a conductive coating. The gap segment, however, is coated by a semiconducting material. The ion gel provides electrical coupling between the gap segment and the gate wire.

A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

Provided is a thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer provided between the gate electrode and the semiconductor layer and formed of an organic polymer compound, and a source electrode and a drain electrode provided in contact with the semiconductor layer and connected via the semiconductor layer, on a substrate, in which the content of metals selected from Mg, Ca, Ba, Al, Sn, Pb, Cr, Mn, Fe, Ni, Cu, Zn, and Ag in the gate insulating layer is 10 ppb to 1 ppm in terms of total amount, or the content of non-metal ionic materials selected from halogen ions, sulfate ions, nitrate ions, and phosphate ions is 1 ppm to 100 ppm in terms of total amount.

A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.

A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.

The present application discloses a method of fabricating an organic thin film transistor comprising providing a substrate; forming a patterned interface modification layer on the substrate; and forming an organic semiconductor layer on a side of the interface modification layer distal to the substrate, wherein the patterned interface modification layer having a pattern of micro structure.

A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.

A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.