Provided is a gated nanostructure device, which includes a thick film comprising a conducting nanoporous material between a source electrode and a drain electrode; and a gate electrode that modulates an electric current through the conducting nanoporous material between the source electrode and the drain electrode throughout a thickness of the thick film. The conducting nanoporous material includes an exposed portion, which is exposed to an external environment, and pores of the conducting nanoporous material are aligned at least partially between the source electrode and the drain electrode.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

The present invention provides a self-healing field-effect transistor (FET) device comprising a self-healing substrate and a self-healing dielectric layer, said substrate and said layer comprising a disulfide-containing poly(urea-urethane) (PUU) polymer, wherein the dielectric layer has a thickness of less than about 10 μm, a gate electrode, at least one source electrode, and at least one drain electrode, said electrodes comprising electrically conductive elongated nanostructures; and at least one channel comprising semi-conducting elongated nanostructures. Further provided is a method for fabricating the FET device.

A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

A transistor device (10) is disclosed comprising a source electrode (14) a drain electrode (12) and an enzyme (31) for facilitating generation of a charge carrier from an analyte. The transistor device also comprises a polymer layer (30) for retaining the enzyme (31), the polymer layer (30) being conductive to the charge carrier. The device also comprises an ohmic conductor (32) in contact with said polymer layer (30) for applying a gate voltage to said polymer layer (30). The device also comprises an organic semiconducting layer (18) connecting the source electrode (14) to the drain electrode (12). Also disclosed is a method of making and using the device (10).

A true random number generator including a transistor, a first voltage source, a second voltage source, and a comparator. The transistor has a first electrode, a second electrode, and a third electrode. Two of the electrodes are electrically connected by a channel of conductive nanomaterial. The first voltage source is electrically connected to the first electrode and the second voltage source is electrically connected to the second electrode. The comparator is electrically connected to the third electrode and is configured to classify a measured electrical property at the third electrode as either HIGH or LOW based on a comparison of the measured electrical property with a reference value. The measured electrical property varies over time due to random telegraph signals (RTSs) due to defects in the transistor.

A compound of Formula 1, as disclosed herein, is useful in an organic light emitting device and apparatuses including the same.

Gated organic light-emitting diodes or vertical light emitting transistors are disclosed based on the modulation of charge carrier injection from electrodes into light-emitting materials by applying external gate potential. This gate modulation were achieved in two disclosed methods: 1) a porous electrode allowing mobile ions to stabilize electrochemically doped semiconducting materials that can form ohmic contact with electrodes: 2) an electrode with gate-tunable work function such as Al:LiF composite electrodes.

A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (L.sub.G) or contact length (L.sub.C). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6 improvement to EDP compared to top-gate CNFETs.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.