A vertical field-effect transistor is provided, comprising a first electrode, a porous conductor layer formed from a layer of conductive material with a plurality of holes extending through the conductive material disposed therein, a dielectric layer between the first electrode and the porous conductor layer, a charge transport layer in contact with the porous conductor layer, and a second electrode electrically connected to the charge transport layer. A photoactive layer may be provided between the dielectric layer and the first electrode. A method of manufacturing a vertical field-effect transistor may also be provided, comprising forming a dielectric layer and depositing a conductor layer in contact with the dielectric layer, wherein one or more regions of the dielectric layer are masked during deposition such that the conductor layer includes a plurality of pores that extend through the conductor layer.

Devices, structures, materials and methods for vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Porous conductive transparent electrodes (such as from nanowires (NW)) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, porous conductive electrodes and relevant substrates and gates are utilized to construct LETs, including singly and doubly gated VPLETs. In addition, printing processes are utilized to deposit layers of one or more of porous conductive electrodes, LEDs, and dielectric materials on various substrates to construct LETs, including singly and doubly gated VPLETs.

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

The present invention relates to a semiconductor structure. The semiconductor structure comprises a semiconductor layer, at least one metallic carbon nanotube, and at least one graphene layer. The semiconductor layer defines a first surface and a second surface opposite to the first surface. The at least one metallic carbon nanotube is located on the first surface of the semiconductor layer. The at least one graphene layer is located on the second surface of the semiconductor layer. The at least one metallic carbon nanotube, the semiconductor layer and the at least one graphene layer are stacked with each other to form at least one three-layered stereoscopic structure. The present invention also relates a semiconductor device, and a photodetector.

Provided is a manufacturing method of a display including a vertical organic light-emitting transistor in which a wider light-emitting area is secured while manufacturing time and manufacturing cost are suppressed. In the manufacturing method of the display including the vertical organic light-emitting transistor, a gate electrode layer of the vertical organic light-emitting transistor and one of current-carrying electrode layers of a thin-film transistor connected to the gate electrode layer of the vertical organic light-emitting transistor are formed integrally in the same layer.

A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

In an embodiment, a transistor device includes: a support layer having a first major surface and a second major surface opposing the first major surface; a source contact arranged on the first major surface of the support layer; a drain contact arranged on the second major surface of the support layer; and a gate electrode arranged in a first trench formed in the first major surface of the support layer. The first trench has a base and a side wall extending from the base to the first major surface. The drain contact is arranged under the base of the first trench. A region with gate-controlled conductivity is formed between the source contact and the drain contact. The region with gate-controlled conductivity is formed in an organic semiconductor layer.

Provided are a display substrate and a preparation method thereof, a display panel, and a display device. The display substrate includes a substrate and a plurality of pixel units on the substrate. The pixel unit comprises a plurality of functional layers that are sequentially arranged in a direction away from the substrate. At least one of the plurality of functional layers, which is close to the substrate, constitutes a vertical thin film transistor (VTFT). At least one of the plurality of functional layers, which is away from the substrate, constitutes an organic light-emitting transistor (OLET). An orthographic projection region of the OLET on the substrate and an orthographic projection region of the VTFT on the substrate at least partially overlap.

The invention refers to a method for producing an organic transistor, the method comprising steps of providing a first electrode (2) on a substrate (1), generating a source-drain insulator (3) assigned at least partially to the substrate (1) and/or at least partially to the first electrode (2), generating a second electrode (4) assigned to the source-drain insulator (3), depositing an organic semiconducting layer (5) on the first electrode (2), the second electrode (4), and the source-drain insulator (3), generating a gate insulator (6) assigned to the organic semiconducting layer (5), and providing a gate electrode (7) assigned to the gate insulator (6). Further, the invention relates to an organic transistor.

A transistor structure is configured as a vertical type transistor. The transistor structure has a patterned electrode located between a gate electrode and a channel region of the transistor structure. The patterned electrode has one or more regions of discontinuity of the electrode. The patterned source electrode has at least two layers having at least a first and second barriers for injection of charge carriers into the channel region. The patterned electrode is configured such that a second layer having a second, higher, barrier for injection of charge carriers is configured to provide a physical barrier for flow of charge carriers from the electrode into the channel region.