The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a dielectric layer having an opening, sidewalls along the opening, a first electrode in the opening, a resistive layer disposed upon the first electrode, an oxygen scavenging layer disposed upon the resistive layer, and a second electrode in contact with the oxygen scavenging layer. The oxygen scavenging layer includes a material that is different from the resistive layer and partially covers the resistive layer. The first electrode is electrically linked to the second electrode by the oxygen scavenging layer and the resistive layer.

An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

A confined phase-change memory cell with self-aligned electrode includes a first conductive structure within a first dielectric layer. A phase-change memory pillar including a first portion of a phase-change material is confined within a second dielectric layer and electrically connected to the first conductive structure. A second conductive structure within a third dielectric layer is surrounded by a second portion of the phase-change material for electrically connecting the second conductive structure to the phase-change memory pillar and reducing heat loss.

A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.

A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.

Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.