The disclosure belongs to the technical field of microelectronic devices and memories, and discloses a three-dimensional stacked phase change memory and a preparation method thereof. The preparation method includes: preparing a multilayer structure in which horizontal electrode layers and insulating layers are alternately stacked, then performing etching to form trenches and separated three-dimensional strip electrodes, next filling the trenches with an insulating medium, and then forming small holes at the boundary region between the three-dimensional strip electrodes and the insulating medium, thereafter sequentially depositing a phase change material on the walls of the small holes, and filling the small holes with an electrode material to prepare vertical electrodes, so as to obtain a three-dimensional stacked phase change memory stacked in multiple layers. By improving the overall process of the preparation method, the disclosure realizes the establishment of a three-dimensional phase change memory array by using a vertical electrode structure.

A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.

Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an are enclosed by the oxide material formed in the opening.

A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

A mixed ionic electron conductor (MIEC)-based memory cell access device is provided. The MIEC-based memory cell access device includes a MIEC material portion located between a bottom electrode and a top electrode. A contact area between the MIEC material portion and the bottom electrode is substantially the same as a contact area between the MIEC material portion and the top electrode.

Discloses is an electronic device and a method for its operation. The device has first and second electrodes and an active material. The active material has selectable and stable first and second macroscopic quantum states, such as charge density wave ordered states, having respectively first and second values of electrical resistivity ρ.sub.1 and ρ.sub.2 at the same temperature. ρ.sub.1 is at least 2 times ρ.sub.2. The method includes the step of switching between the first and second macroscopic quantum states by injection of current via the electrodes.

In accordance with an example embodiment of the present invention, an apparatus is disclosed. The apparatus includes a resistive memory component including an active material and two or more electrodes in electrical contact with the active material of the resistive memory component; and a selector component providing control over the resistive memory component, the selector component including an active material and two or more electrodes in electrical contact with the active material of the selector component. The resistive memory component and the selector component share one or more electrodes, and the resistive memory component and the selector component share at least part of the active material. A method and apparatus for producing the apparatus are also disclosed.

A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.