A plurality of memory cells in a 3D cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.

A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.

An embodiment of the invention may include a semiconductor structure. The semiconductor structure may include a phase change element located above a heater. The heater may include a conductive element surrounding a dielectric element. The dielectric element may include an air gap.

A method of manufacturing an electronic device comprises: forming a plurality of line patterns on a substrate extending in a first direction and including a first conductive line and a memory pattern; forming a first liner layer on sidewalls of each of the plurality of line patterns, the first liner layer including a plurality of layers having different energy band gaps; forming an insulating interlayer on the substrate; forming a plurality of second conductive lines on the line patterns and the insulating interlayer; etching the first liner layer, the insulating interlayer and the memory pattern using the second conductive lines as an etch barrier to expose the first conductive line to form a plurality of memory cells; and forming a second liner layer on both sidewalls of each of the memory cells, the etched first liner layer and both sidewalls of the etched insulating interlayer.

A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

The present invention discloses a method for manufacturing a phase change memory and a phase change memory. The method comprises: forming a first wafer having a semiconductor-on-insulator structure; forming a memory material layer on the semiconductor-on-insulator structure; and forming a first metal material layer on the memory material layer to form a first semiconductor element.

In fabrication of a phase change random access memory (PCRAM), a field effect transistor (FET) logic layer is formed on a first wafer, including a heating FET for each storage cell. The FET logic layer is transferred from the first wafer to a carrier wafer. Thereafter, a storage layer of the PCRAM is formed on the exposed surface of the FET logic layer, including a region of a phase change material for each storage cell that is electrically connected to a channel of the heating FET of the storage cell. The storage layer further includes a second heating transistor for each storage cell that is electrically connected to a channel of the second heating transistor.

The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.