Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.

A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

Various embodiments may provide an electronic synapse device. The electronic synapse device may include a body including a doped chalcogenide layer including a chalcogenide material and a dopant. The electronic synapse device may also include a drain electrode in contact with the body. The electronic synapse device may further include a source electrode in contact with the body. The electronic synapse device may additionally include a gate electrode including an electrode contact layer in contact with the doped chalcogenide layer. The electrode contact layer may be any one selected from a group consisting of an electrically conductive layer including an electrically conductive material and a dopant layer including the dopant.

A method of forming a phase change switching device includes providing a substrate, forming first and second RF terminals on the substrate, forming a strip of phase change material on the substrate that is connected between the first and second RF terminals, forming a heating element adjacent to the strip of phase change material such that the heating element is configured to control a conductive state of the strip of phase change material. The first and second RF terminals and the heating element are formed by a lithography process that self-aligns the heating element with the first and second RF terminals

Provided herein are novel materials, such as novel phase-change memory materials providing superior characteristics, and methods of discovering/selecting such novel materials via machine learning, such as Bayesian active learning. An exemplary material provided by the inventive concept is the nanocomposite phase-change memory material Ge.sub.4Sb.sub.6Te.sub.7, selected using closed-loop autonomous materials exploration and optimization (CAMEO).

A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.

Provided are a chalcogenide material, and a device and a memory device each including the same. The chalcogenide material may include: germanium (Ge) as a first component; arsenic (As) as a second component; at least one element selected from selenium (Se) and tellurium (Te) as a third component; and at least one element selected from the elements of Groups 2, 16, and 17 of the periodic table as a fourth component, wherein a content of the first component may be from 5 at % to 30 at %, a content of the second component may be from 20 at % to 40 at %, a content of the third component may be from 25 at % to 75 at %, and a content of the fourth component may be from 0.5 at % to 5 at %.

Technologies for reducing series resistance are disclosed. An example method may comprise: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.