A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.

A memory device includes a first interconnect layer, a second interconnect layer, a phase-change layer, and an adjacent layer. The phase-change layer is disposed between the first interconnect layer and the second interconnect layer and configured to reversibly transition between a crystalline state and an amorphous state. The adjacent layer contacts the phase-change layer and comprises tellurium and at least one of titanium, zirconium, or hafnium.

A storage device 10 includes a phase change layer 40 containing tellurium, and a diffusion layer 50 containing at least one of germanium, silicon, carbon, tin, aluminum, gallium, and indium and disposed at a position adjacent to the phase change layer 40. The phase change layer 40 is capable of changing between a first state and a second state different from each other in electric resistance. The phase change layer 40 is in a crystal state in any of the first state and the second state. A length of the diffusion layer 50 in a direction orthogonal to a z direction is shorter than a length of the phase change layer 40 in the direction orthogonal to the z direction.

A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

An electronic device comprises a semiconductor memory that includes: a memory cell; a protective layer disposed along a profile of the memory cell; and a buffer layer interposed between at least a portion of a sidewall of the memory cell and the protective layer, wherein the buffer layer and the protective layer include silicon nitride, and wherein a density of the protective layer is greater than a density of the buffer layer.

A method for manufacturing a nonvolatile semiconductor storage device includes: forming a first conductive layer by self-alignment on a first wiring layer, and performing an annealing processing; stacking a first stacked film on the first conductive layer; processing the first stacked film, the first conductive layer, and the first wiring layer into a stripe structure extending in a first direction; forming and planarizing a first interlayer insulating film; forming a second wiring layer; forming a second conductive layer by self-alignment on the second wiring layer, and performing an annealing processing; processing the second wiring layer and the second conductive layer into a stripe structure extending in a second direction intersecting the first direction; and processing the first stacked film and the first interlayer insulating film below and between the second wiring layer, and forming a first memory cell having the first stacked film in a columnar shape.

Disclosed is a reconfigurable transistor device having a substrate, a plurality of first transistor fingers disposed in a first region over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate in a second region to selectively couple a first set of the plurality of first transistor fingers to a bus, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the first thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.

Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.