An approach to provide a semiconductor structure for an array of individual memory cells forming a crossbar array. A plurality of individual memory cells where each memory cell on a first metal layer includes a top electrode contact and a bottom electrode contact in a second metal layer. The crossbar array includes a word line above each of the individual memory cells connecting one or more adjacent top electrode contacts and a bit line above each of the individual memory cells connecting one or more of the adjacent bottom electrode contacts where each memory cell of the plurality of memory cells has a pre-formed conductive filament in a resistive switch device in each memory cell.

A resistive random access memory array includes a plurality of memory cells. Each memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element. The resistive random access memory array is used to generate physical unclonable function data.

A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

A non-volatile memory device is provided. The nonvolatile memory device includes a metal pillar, a channel layer separated from the metal pillar and surrounding a side surface of the metal pillar, a source arranged on one end of the channel layer, a drain arranged on the other end of the channel layer, a gate insulating layer surrounding a side surface of the channel layer, and a plurality of insulating elements and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer and surrounding a side surface of the gate insulating layer.

A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer extending in a first direction; a plurality of gates and a plurality of insulators alternately arranged in the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide.

An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having a spacer element on a side of the electrode. The present disclosure provides a memory device including a first electrode having a side, the side has upper and lower portions, a spacer element on the lower portion of the side of the first electrode, a resistive layer on the upper portion of the side of the first electrode, and a second electrode laterally adjacent to the side of the first electrode. The second electrode has a top surface, in which the top surface has a concave profile.