A memory device may include a bank layer and a control circuit layer. The bank layer may be arranged on a semiconductor substrate. The bank layer may include a plurality of mats. Each of the mats may include a plurality of stacked decks. Each of the decks may include a plurality of memory cells. The control circuit layer may be arranged between the semiconductor substrate and the bank layer. The control circuit layer may include a plurality of control circuit regions corresponding to the mats, respectively. The stacked decks may include a plurality of stacked word lines and a plurality of stacked bit lines intersected with the stacked word lines. A word line decoder, for controlling the word lines, and a bit line decoder, for controlling the bit lines, may be alternately and repeatedly arranged in the control circuit layer.

The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (Φ.sub.B) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (Φ.sub.T) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.

An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F.sup.2 may be realized.

The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.

A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure in which cations are disordered, and contains a divalent cation of a non-magnetic element, a trivalent cation of a non-magnetic element, oxygen, and one of nitrogen and fluorine.

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

The present disclosure relates to a memory device. The memory device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate increases.

A nonvolatile memory device according to an embodiment includes a substrate, and a gate structure disposed on the substrate and including a hole pattern. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer which are alternately stacked, and the gate electrode layer protrudes toward a center of the hole pattern relative to the interlayer insulation layer. The nonvolatile memory device includes a first functional layer disposed along a sidewall surface of the gate structure inside the hole pattern, a second functional layer disposed on the first functional layer inside the hole pattern, and a channel layer extending in a direction perpendicular to the substrate inside the hole pattern and disposed to contact a cell portion of the second functional layer. The cell portion of the second functional layer indirectly covers a sidewall surface of the gate electrode layer.

A system may include an array of interconnected memristors. Each memristor may include a first electrode, a second electrode, and a memristor material positioned between the first electrode and the second electrode. The system may further include a controller communicatively coupled to the array of interconnected memristors. The controller may be configured to tune the array of interconnected memristors.