A non-volatile memory structure may include a phase change memory comprising a phase change material. The non-volatile memory structure may include a Schottky diode in series with the phase change memory, wherein a Schottky barrier of the Schottky diode is a surface of the phase change memory. This may be accomplished through a proper selection of materials for the contact of the phase change memory. This may create an integrated diode-memory structure which may control directionality of current without a penalty on the footprint of the structure.

The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.

A selection device and a crosspoint memory including the same are provided. The selection device has a lower electrode. A polycrystalline metal oxide layer including insulating crystal grains and a conductive nanochannel formed in a grain boundary between the crystal grains is disposed on the lower electrode. An upper electrode is disposed on the polycrystalline metal oxide layer.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.

A resistive memory device includes a vertical word line pillar, a plurality of resistive layers, a gate insulation layer, and a channel layer. The vertical word line pillar is formed on a semiconductor substrate. The resistive layers are stacked at both sides of the vertical word line pillar. The gate insulation layer is interposed between the vertical word line pillar and the resistive layers. The channel layer is arranged between the gate insulation layer and the resistive layers.

Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

A resistance random access memory device includes a resistance change layer, including an organometallic halide having perovskite grains, disposed on a first electrode; and a second electrode disposed on the resistance change layer. A boundary between the perovskite grains comprises an amorphous metal oxide.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M.sup.2<2×N×k is satisfied.