A memory structure is provided. The memory structure includes a top terminal, a multi-level nonvolatile electrochemical cell, a bottom terminal, a pedestal contact in the same metal level as the bottom terminal, and a vertical conductor fully self-aligned to the multi-level nonvolatile electrochemical cell and extending vertically from the pedestal contact.

A photovoltaic device having a perovskite PV cell wherein the PV device operates, for example during start-up, initially in a bias-voltage operating mode, in which a bias voltage is applied to the perovskite PV cell of the PV device. The bias voltage or the energy needed for same can advantageously be drawn from the power electronics associated with the perovskite PV cell.

Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

This semiconductor device comprises an active layer that is formed of an oxide magnetic material and a porous dielectric body that contains water and is provided on the active layer. By using hydrogen and oxygen which are formed by electrolysis of water, the crystal structure of the active layer is changed between a ferromagnetic metal and an antiferromagnetic insulating body.

Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.

The present invention discloses a memory cell that includes at least two non-volatile resistive memory elements coupled in parallel. The non-volatile resistive memory elements are capable of existing in different resistive states such that each of the different resistive state represents a different data state. The non-volatile resistive memory elements may include multiple layers formed within contact holes.

A method for fabricating an electronic device including a semiconductor memory includes: forming a memory layer over a substrate; forming a memory element by selectively etching the memory layer, wherein forming the memory element includes forming an etching residue on a sidewall of the memory element, the etching residue including a first metal; and forming a spacer by implanting oxygen and a second metal into the etching residue, the spacer including a compound of the first metal-oxygen-the second metal, the second metal being different from the first metal.