A method of manufacturing a semiconductor device comprises: providing a substrate having a base insulation layer; forming, over the base insulation layer, a plurality of first word line structures extending in a first lateral direction and a first switching functional layer disposed between the plurality of first word line structures, the plurality of first word line structures; forming a first interlayer insulation layer on the plurality of first word line structures and the first switching functional layer; forming a plurality of second word line structures and a second switching functional layer disposed between the plurality of second word line structures; performing selective etching to the second switching functional layer, the first interlayer insulation layer, the first switching functional layer, and the base insulation layer to form bit line contact holes; and providing a conductive material in the bit line contact holes to form bit line structures.

A phase-change material (PCM) includes elements in a composition of germanium Ge from 9 to 14 at %, antimony Sb from 15 to 22 at %, tellurium Te from 44 to 55 at %, silicon Si from 5.5 to 9 at %, and carbon C from 14.5 to 20 at %. It has a crystallization transition temperature higher than 250° C., a crystallization time of less than 200 ns, and an endurance above ten million (10.sup.7) write cycles. A memory device includes the PCM, and the PCM has a thickness below 100 nm. Memory elements including the PCM are arranged in an array to form a crosspoint memory, or in a stack of two or more arrays to form a 3D crosspoint memory. The memory elements may each include the PCM, a buffer layer, and a selector device.

A non-volatile memory circuit in embodiments of the present invention may have one or more of the following features: (a) a logic source, and (b) a semi-conductive device being electrically coupled to the logic source, having a first terminal, a second terminal and a nano-grease with significantly reduced amount of carbon nanotube loading located between the first and second terminal, wherein the nano-grease exhibits non-volatile memory characteristics.

A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M.sup.2<2×N×k is satisfied.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.

Two-terminal nanotube switching devices employing nanotube fabrics configured with breaks among the nanotube elements and methods of making such devices are disclosed. Breaks within the nanotube elements can be formed by applying a sufficiently high voltage or a sufficiently high electrical current through the nanotube fabric. These breaks within the individual nanotube elements realize switching sites within the fabric which provide uniform and controllable characteristics for the nanotube switching device.

Techniques for semiconductor devices including amorphous silicon are disclosed. In the illustrative embodiment, trenches are etched through several layers of a memory during manufacture, including through a phase-change layer. To protect the phase-change layer during further processing steps, amorphous silicon is applied to the phase-change layer using low-temperature chemical vapor deposition, which can be done without exceeding the melting point of the phase-change layer. The amorphous silicon can be oxidized, forming a protective silicon oxide layer around the phase-change layer.

A method to fabricate a resistive change element array may include depositing a resistive change material over a substrate and forming a first insulating material over the resistive change material. The method may also include etching a trench in the resistive change material and the first insulating material and forming a cavity in a sidewall of the trench by recessing the resistive change material. The method may further include flowing a conductive material in the cavity and depositing a second insulating material in the trench.

An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.

A method to fabricate a resistive change element array may include depositing a resistive change material over a substrate and forming a first insulating material over the resistive change material. The method may also include etching a trench in the resistive change material and the first insulating material and forming a cavity in a sidewall of the trench by recessing the resistive change material. The method may further include flowing a conductive material in the cavity and depositing a second insulating material in the trench.