H10N70/8845

Microswitch and electronic device in which same is used

Provided is a microswitch including a first electrode, a second electrode, and a porous coordination polymer conductor, in which the porous coordination polymer conductor is represented by the following Formula (1), and a metal forming the first electrode and a metal forming the second electrode have different oxidation-reduction potentials,
[ML.sub.x].sub.n(D).sub.y  (1), where M represents a metal ion selected from group 2 to group 13 elements in a periodic table, L represents a ligand that has two or more functional groups capable of coordination to M in a structure of L and is crosslinkable with two M's, D represents a conductivity aid that includes no metal element, x represents 0.5 to 4 and y represents 0.0001 to 20 with respect to x as 1, n represents the number of repeating units of a constituent unit represented by [ML.sub.x], and n represents 5 or more.

Memory device
11069745 · 2021-07-20 · ·

According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

Memory cell and forming method thereof

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

PHASE CHANGE MEMORY WITH A CARBON BUFFER LAYER

A memory element comprises a carbon deposit, such as a carbon buffer layer, on a body of phase change memory material, disposed between first and second electrodes. A carbon deposit is found to improve endurance of phase change memory cells by five orders of magnitude or more. Examples include “mushroom” style memory elements, as well as other types including 3D arrays of cross-point elements.

Switch Cell Device
20210257534 · 2021-08-19 ·

Various implementations described herein are related to a device having multiple conductive terminals formed with a superconductive material. The device may include at least one switching layer formed with correlated-electron material (CEM) that is disposed between the multiple conductive terminals. The CEM may comprise carbon or a carbon based compound. The device may refer to a switch structure or similar.

Storage device

A storage device includes a first conductor, a second conductor, a variable resistance layer, a first portion, and a second portion. The variable resistance layer connects with the first conductor or the second conductor. The first portion is provided between the first conductor and the second conductor, and has a first threshold voltage value at which the resistance value changes. The second portion is provided between the first conductor and the first portion and/or between the second conductor and the first portion, and has a second threshold voltage value at which the resistance value changes and which is higher than the first threshold voltage value.

MICROSWITCH AND ELECTRONIC DEVICE IN WHICH SAME IS USED

Provided is a microswitch including a first electrode, a second electrode, and a porous coordination polymer conductor, in which the porous coordination polymer conductor is represented by the following Formula (1), and a metal forming the first electrode and a metal forming the second electrode have different oxidation-reduction potentials,


[ML.sub.x].sub.n(D).sub.y  (1),

where M represents a metal ion selected from group 2 to group 13 elements in a periodic table, L represents a ligand that has two or more functional groups capable of coordination to M in a structure of L and is crosslinkable with two M's, D represents a conductivity aid that includes no metal element, x represents 0.5 to 4 and y represents 0.0001 to 20 with respect to x as 1, n represents the number of repeating units of a constituent unit represented by [ML.sub.x], and n represents 5 or more.

ELASTIC STRAIN ENGINEERING OF DEFECT DOPED MATERIALS

Compositions and methods related to straining defect doped materials as well as their methods of use in electrical circuits are generally described.

Elastic strain engineering of defect doped materials

Compositions and methods related to straining defect doped materials as well as their methods of use in electrical circuits are generally described.

ELEMENTARY CELL COMPRISING A RESISTIVE MEMORY AND ASSOCIATED METHOD OF INITIALISATION
20210184117 · 2021-06-17 ·

An aspect of the invention relates to an elementary cell that includes a breakdown layer made of dielectric having a thickness that depends on a breakdown voltage, a device and a non-volatile resistive memory mounted in series, the device including an upper selector electrode, a lower selector electrode, a layer made in a first active material, referred to as active selector layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made in at least one second active material, referred to as active memory layer.