A sputtering chamber particle trap comprises first and second patterns formed on at least a portion of a surface of the particle trap. The first pattern includes one of: first indentations having a first depth and separated by first and second threads, and first ridges having a first height and separated by first and second grooves. The second pattern is formed on at least a portion of the first pattern and includes one of: second indentations having a second depth and separated by third and fourth threads, and second ridges having a second height and separated by third and fourth grooves. A method of forming a particle trap on a sputtering chamber component is also disclosed.

Exemplary processing methods may include forming a plasma of a cleaning precursor in a remote region of a semiconductor processing chamber. The methods may include flowing plasma effluents of the cleaning precursor into a processing region of the semiconductor processing chamber. The methods may include contacting a substrate support with the plasma effluents for a first period of time. The methods may include lowering the substrate support from a first position to a second position while continuing to flow plasma effluents of the cleaning precursor. The methods may include cleaning the processing region of the semiconductor processing chamber for a second period of time.

The present invention provides a method for using ion filtering to adjust the number of ions delivered to a substrate. The method comprising a process chamber being provided that is operatively connected to a plasma source. The substrate is provided on a substrate support that is provided within the process chamber. An electrical bias source is provided that is operatively connected to an aperture plate that is provided in the process chamber. The substrate on the substrate support is processed using a plasma generated using the plasma source. A variable bias voltage from the electrical bias source is applied to the aperture plate during the plasma processing of the substrate. The plasma processing of the substrate can further comprise exposing the substrate to a plasma time division multiplex process which alternates between deposition and etching on the substrate.

A plasma processing apparatus includes: a processing container in which a mounting stage mounted with a substrate is provided and a plasma process is performed on the substrate; an exhaust passage which is provided around the mounting stage and through which a gas containing a by-product released by the plasma process flows; and a first adsorption member which is arranged along an inner wall surface of the exhaust passage and of which a surface is roughened to adsorb the by-product.

In some embodiments, the present disclosure relates to a method of performing an etching process. The method includes generating a plasma within a plasma chamber in communication with a processing chamber. Ions from the plasma are accelerated toward a workpiece within the processing chamber to generate an ion beam. The ion beam performs an etching process that etches a material on the workpiece. A by-product from the etching process is moved to directly below one or more baffles within the processing chamber.

The invention provides a collection assembly and a semiconductor pre-cleaning chamber, which relate to the semiconductor processing apparatus field. The collection assembly is configured to collect particle impurities in the semiconductor pre-cleaning chamber, and includes a protection plate and a collection plate arranged at an interval in the semiconductor pre-cleaning chamber. The protection plate is annular. A plurality of first through-holes are arranged at the protection plate and configured for the process gas in the semiconductor pre-cleaning chamber to pass through. The collection plate is located on a side of an air outlet end of the first through-holes and configured to capture at least a part of the particle impurities in the semiconductor pre-cleaning chamber passing through the first through-holes.

A method for altering surface charge on an insulating surface of a first sample includes generating first plasma inside a plasma source, causing the first plasma to diffuse into a first vacuum chamber to generate second downstream plasma, immersing the first sample in the second downstream plasma, and applying a first bias voltage to a conductive layer of the first sample, or applying a first bias voltage to a metal holder that holds the first sample.

A plasma processing apparatus includes: a processing container in which a mounting stage mounted with a substrate is provided and a plasma process is performed on the substrate; an exhaust passage which is provided around the mounting stage and through which a gas containing a by-product released by the plasma process flows; and a first adsorption member which is arranged along an inner wall surface of the exhaust passage and of which a surface is roughened to adsorb the by-product.

Embodiments herein include a transparent halo assembly for reducing an amount of sputtered material to minimize particle defects impacting a workpiece. In some embodiments, a halo assembly may include a first halo arranged around a semiconductor workpiece, and a mounting assembly coupling the first halo to a roplat. The first halo may include a first side opposite a second side, and a first end opposite a second end, wherein the first side is operable to receive an ion beam from an ion source. The first halo may further include a plurality of apertures extending between the first and second sides, wherein the plurality of apertures permit passage of a portion of the ion beam to pass therethrough, towards the mounting assembly. In some embodiments, the halo assembly may include a second halo positioned proximate the first halo, and a third halo disposed between the first halo and the mounting assembly.

Various carrier ring designs and configurations to control an amount of deposition at a wafer's front side and bevel edge are provided. The carrier ring designs can control the amount of deposition at various locations of the wafer while deposition is performed on the wafer's back side, with no deposition desired on the front side of the wafer. These locations include front side, edge, and back side of bevel; and front and back side of the wafer. Edge profiles of the carrier rings are designed to control flow of process gases, flow of front side purge gas, and plasma effects. In some designs, through holes are added to the carrier rings to control gas flows. The edge profiles and added features can reduce or eliminate deposition at the wafer's front side and bevel edge.