In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.

Optimization techniques are disclosed for producing sharp and stable tips/nanotips relying on liquid Taylor cones created from electrically conductive materials with high melting points. A wire substrate of such a material with a preform end in the shape of a regular or concave cone, is first melted with a focused laser beam. Under the influence of a high positive potential, a Taylor cone in a liquid/molten state is formed at that end. The cone is then quenched upon cessation of the laser power, thus freezing the Taylor cone. The tip of the frozen Taylor cone is reheated by the laser to allow its precise localized melting and shaping. Tips thus obtained yield desirable end-forms suitable as electron field emission sources for a variety of applications. In-situ regeneration of the tip is readily accomplished. These tips can also be employed as regenerable bright ion sources using field ionization/desorption of introduced chemical species.

An electron source is formed on a silicon substrate having opposing first and second surfaces. At least one field emitter is prepared on the second surface of the silicon substrate to enhance the emission of electrons. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitter using a process that minimizes oxidation and defects. The field emitter can take various shapes such as pyramids and rounded whiskers. One or several optional gate layers may be placed at or slightly lower than the height of the field emitter tip in order to achieve fast and accurate control of the emission current and high emission currents. The field emitter can be p-type doped and configured to operate in a reverse bias mode or the field emitter can be n-type doped.

Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.

A package having a field emission element may include a handle layer; a buried layer stacked on the handle layer; a device layer stacked on the buried layer; an insulating layer stacked in an upper region of the device layer; a gate electrode stacked in an upper region of the insulating layer; and at least one light-emitting element disposed in a lower region of the device layer, and configured to emit light through the device layer. The insulating layer may be configured with a plurality of insulating regions separated by first separation regions, and the gate electrode may be configured with a plurality of metal regions separated by second separation regions. The device layer may be provided with protruding portions disposed to protrude between the first separation regions between the insulating regions and the second separation regions between the metal regions.

A backend field emission device may include a field emission device in a backend of line (BEOL) layer, such as an interconnect layer. In one example, a backend field emission device includes a first electrode coupled with a first conductive interconnect, a second electrode coupled with a second conductive interconnect, an airgap between the first electrode and the second electrode, and a third electrode between the first electrode and the second electrode and coplanar with the airgap.