A charged particle beam lithography apparatus, includes a plurality of multiple-beam sets, each of which including a plurality of irradiation sources each generating an independent charged particle beam, a plurality of objective deflectors, each arranged for a corresponding charged particle beam, and configured to deflect the corresponding charged particle beam to a desired position on a substrate, and a plurality of electrostatic or electromagnetic lens fields each to focus the corresponding charged particle beam on the target object; a plurality of common deflection amplifiers, arranged for each multiple-beam set, and each of the plurality of common deflection amplifiers being configured to commonly control the plurality of objective deflectors arranged in a same multiple-beam set; a plurality of individual ON/OFF mechanisms configured to individually turn ON/OFF a beam irradiated from each irradiation source; and one or more multiple-beam clusters including the plurality of multiple-beam sets.

A charged particle beam lithography apparatus, includes a plurality of multiple-beam sets, each of which including a plurality of irradiation sources each generating an independent charged particle beam, a plurality of objective deflectors, each arranged for a corresponding charged particle beam, and configured to deflect the corresponding charged particle beam to a desired position on a substrate, and a plurality of electrostatic or electromagnetic lens fields each to focus the corresponding charged particle beam on the target object; a plurality of common deflection amplifiers, arranged for each multiple-beam set, and each of the plurality of common deflection amplifiers being configured to commonly control the plurality of objective deflectors arranged in a same multiple-beam set; a plurality of individual ON/OFF mechanisms configured to individually turn ON/OFF a beam irradiated from each irradiation source; and one or more multiple-beam clusters including the plurality of multiple-beam sets.

A scalable, integrated multi-level photoemitter device of tapered design and method of manufacture using conventional CMOS manufacturing techniques. The photoemitter device has a tapered multi-level structure formed in a material layer of a substrate, each level comprising a layer of photoemissive material and a connecting portion, said connecting portion for connecting to an adjacent photoemissive material layer of a next successive level. A first photoemissive material layer of a first level is of a configuration having a first length or width dimension; and each successive layer includes a photoemissive material layer of successively smaller length or width dimensions