An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

A semiconductor manufacturing apparatus includes: a stage installed inside a processing chamber and holding a semiconductor substrate having a high-k insulating film including silicate; and a gas supply line including a first system supplying reactive gas to the processing chamber and a second system supplying catalytic gas to the processing chamber, wherein mixed gas which includes complex forming gas reacting with a metal element included in the high-k insulating film to form a first volatile organometallic complex and complex stabilizing material gas increasing stability of the first organometallic complex is supplied as the reactive gas, and catalytic gas using a second organometallic complex, which modifies the high-k insulating film and promotes a formation reaction of the first organometallic complex, as a raw material is supplied.

A method for fabricating a capacitor includes forming a first electrode, forming a dielectric layer stack on the first electrode, the dielectric layer stack including an initial hafnium oxide layer and a seed layer having a doping layer embedded therein, forming a thermal source layer on the dielectric layer stack to crystallize the initial hafnium oxide into tetragonal hafnium oxide, and forming a second electrode on the thermal source layer.

There is provided a technique that includes (a) forming a first film having a first thickness on an underlayer by supplying a first process gas not including oxidizing gas to a substrate, wherein the first film contains silicon, carbon, and nitrogen and does not contain oxygen, and the underlayer is exposed on a surface of the substrate and is at least one selected from the group of a conductive metal-element-containing film and a nitride film; and (b) forming a second film having a second thickness larger than the first thickness on the first film by supplying a second process gas including oxidizing gas to the substrate, wherein the second film contains silicon, oxygen, and nitrogen, and wherein in (b), oxygen atoms derived from the oxidizing gas and diffuse from a surface of the first film toward the underlayer are absorbed by the first film and the first film is modified.

A capacitor is provided for high temperature systems. The capacitor includes: a substrate formed from silicon carbide material; a dielectric stack layer, including a first layer deposited on the substrate and a second layer deposited on the first layer; a Schottky contact layer deposited on the second layer; and an Ohmic contact layer deposited on the substrate. The first layer is formed with aluminum nitride (AlN) epitaxially, and the second layer is formed with aluminum oxide (Al.sub.2O.sub.3). AlN and Al.sub.2O.sub.3 are ultrawide band gap materials, and as a result, they can be use as the dielectric in the capacitor, allowing the capacitance changes to be less than 10% between −250° C. and 600° C., which is very effective for the high temperature systems.

Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

A film forming method includes: rotating a rotary table to revolve a substrate which is placed on the rotary table and has a recess in its surface; supplying a raw material gas to a first region on the rotary table; supplying an ammonia gas to a second region on the rotary table; forming a first SiN film in the recess by supplying the raw material gas to the first region and supplying the ammonia gas to the second region at a first flow rate, while the rotary table rotates at a first rotation speed; and forming a second SiN film in the recess such that the second SiN film is laminated on the first SiN film by supplying the raw material gas to the first region and supplying the ammonia gas to the second region at a second flow rate, while the rotary table rotates at a second rotation speed.

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

A method for fabricating a capacitor includes forming a first electrode, forming a dielectric layer stack on the first electrode, the dielectric layer stack including an initial hafnium oxide layer and a seed layer having a doping layer embedded therein, forming a thermal source layer on the dielectric layer stack to crystallize the initial hafnium oxide into tetragonal hafnium oxide, and forming a second electrode on the thermal source layer.

Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.