A method of treating a semiconductor substrate includes converting a first main side of the semiconductor substrate having a first coefficient of static friction relative to a surface of a wafer table to a second coefficient of static friction relative to the surface of the wafer table, wherein the second coefficient of static friction is less than the first coefficient of static friction. A photoresist layer is applied over a second main side of the semiconductor substrate having the first coefficient of static friction. The second main side opposes the first main side. The semiconductor substrate is placed on the wafer table so that the first main side of the semiconductor substrate faces the wafer table.

A method for filling a gap feature on a substrate surface is disclosed. The method may include: providing a substrate comprising a non-planar surface including one or more gap features; depositing a metal oxide film over a surface of the one or more gap features by a cyclical deposition process; contacting the metal oxide with an organic ligand vapor; and converting at least a portion of the metal oxide film to a porous material thereby filling the one or more gap features. Semiconductor structures including a metal-organic framework material formed by the methods of the disclosure are also disclosed.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

A method for shallow etching a substrate surface forms a shallow modified substrate layer overlying unmodified substrate using an accelerated neutral beam and etches the modified layer, stopping at the unmodified substrate beneath, producing controlled shallow etched substrate surfaces.

In a first aspect, the present disclosure relates to a method for removing an organic sacrificial material from a 2D material, comprising: providing a target substrate having thereon the 2D material and a layer of the organic sacrificial material over the 2D material, infiltrating the organic sacrificial material with a metal or ceramic material, and removing the organic sacrificial material.

A structure body includes a base material and a siloxane based molecular membrane formed on the base material by use of an organic compound represented by Formula (1) or Formula (2):

##STR00001##

wherein any one of R1 to R5 is an amino group, others of R1 to R5 are each independently hydrogen or an alkyl group, R7 to R9 are each independently any one of hydroxy group, alkoxy group, alkyl group, and phenyl group on condition that one or more of R7 to R9 are each independently a hydroxy group or an alkoxy group, and R6 is an alkyl group.

Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.

A semiconductor device and a manufacture method of the semiconductor device are provided. In the semiconductor device, a back surface of a substrate is covered with a first insulating layer, where the first insulating layer covers the bottom and the sidewall of a through hole and the back surface of the substrate outside the through hole. The first insulating layer outside the through hole is covered with a second insulating layer. When etching the first insulating layer at the bottom of the through hole, although an etching speed for a region outside the through hole is greater than an etching speed for the bottom of the through hole, the first insulating layer outside the through hole is protected from being over-etched by the second insulating layer, which improves reliability of the device.