Photovoltaics configured to be manufactured without epitaxial processes and methods for such manufacture are provided. Methods utilize bulk semiconducting crystal substrates, such as, for example, GaAs and InP such that epitaxy processes are not required. Nanowire etch and exfoliation processes are used allowing the manufacture of large numbers of photovoltaic cells per substrate wafer (e.g., greater than 100). Photovoltaic cells incorporate electron and hole selective contacts such that epitaxial heterojunctions are avoided during manufacture.

A method includes forming a first layer and a second layer on a substrate, forming a passivation layer on a surface of the first layer without forming the passivation layer on a surface of the second layer by exposing the first layer and the second layer to a benzyl compound, and after forming the passivation layer on the first layer, performing at least one of: depositing a third layer on the second layer, or etching the second layer.

Electronic device packages utilizing a stiffener coupled to a substrate with a magnetic lossy bonding layer to attenuate or absorb electromagnetic signals such as radio frequency interference (RFI) along with related systems and method are disclosed.

Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.

Method of doping a semiconductor sample in a uniform and carbon-free way, wherein said sample has a surface, comprising the following steps: A. removing oxides from at least part of the said surface; B. dip coating said at least part of the surface of the sample in a dopant based carbon-free solution of at least one dopant based carbon free substance diluted in water, wherein said at least one dopant based carbon free substance has a molecule comprising at least one dopant atom, wherein the dip coating is achieved by heating said dopant based carbon-free solution at a dip coating temperature from 65% to 100% of the boiling temperature of said dopant based carbon-free solution, thereby a self-assembled mono-layer including dopant atoms is formed; C. annealing said sample, wherein the annealing is configured to cause said dopant atoms included in said self-assembled mono-layer to be diffused into the sample.

Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.

Methods for forming a titanium-containing hard mask film on a substrate surface by exposing the substrate surface to a titanium-containing precursor. The titanium-containing hard mask comprises one or more of silicon, oxygen or carbon atoms and, optionally, nitrogen atoms.

A semiconductor device and a manufacture method of the semiconductor device are provided. In the semiconductor device, a back surface of a substrate is covered with a first insulating layer, where the first insulating layer covers the bottom and the sidewall of a through hole and the back surface of the substrate outside the through hole. The first insulating layer outside the through hole is covered with a second insulating layer. When etching the first insulating layer at the bottom of the through hole, although an etching speed for a region outside the through hole is greater than an etching speed for the bottom of the through hole, the first insulating layer outside the through hole is protected from being over-etched by the second insulating layer, which improves reliability of the device.

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.