Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

A device includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a metrology module configured to measure wafer shape data of a first wafer and a second wafer, including relative z-height values of the first wafer and the second wafer. A stressor film deposition module is configured to form a first stressor film on the first wafer. A stressor film modification module is configured to modify the first stressor film based on a first modification map that defines adjustments to internal stresses of the first wafer and is generated based on the wafer shape data. The second set of modules includes an alignment module configured to align the first wafer with the second wafer, and a bonding module configured to bond the first wafer to the second wafer.

A photovoltaic device comprises plural layers separated into plural cells, each comprising a region of a photoactive layer and electrodes on opposite sides thereof. Each of the regions of the photoactive layer are formed comprising a first part that comprises photoactive material and a second part that is not photoactive and that has a greater transmittance of visible light than the light absorbing photoactive material, in pre-selected locations, or in a pre-selected distribution of locations, across the region of the photoactive layer. One of the first and second parts are located in plural separate areas within the other of the first and second parts. The transparency of the photovoltaic device is increased by the transmission of light through the second part that is not photoactive.

Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

A method, for bonding a first wafer to a second wafer, includes generating a first modification map based on wafer shape data of the first wafer and the second wafer. The first modification map defines adjustments to internal stresses of the first wafer. A first wafer shape of the first wafer is modified by forming a first stressor film on the first wafer based on the first modification map. The first wafer is aligned with the second wafer after the modifying. The first wafer is bonded to the second wafer.

A method includes: forming a dummy gate dielectric layer over a channel region of a fin structure; forming a dummy gate over the dummy gate dielectric layer; removing the dummy gate and a first portion of the dummy gate dielectric layer to expose the channel region of the fin structure; removing a first nanowire of the fin structure above a second nanowire of the fin structure to remain the second nanowire of the fin structure; forming an interfacial layer surrounding the second nanowire; forming a material layer comprising dopants over the interfacial layer; and performing an annealing process to drive the dopants of the material layer into the interfacial layer, thereby forming a doped interfacial layer surrounding the second nanowire.

A method comprises transporting a first stream of a carrier gas to a delivery device that contains a liquid precursor compound. The method further comprises transporting a second stream of the carrier gas to a point downstream of the delivery device. The first stream after emanating from the delivery device and the second stream are combined to form a third stream, such that the dew point of the vapor of the liquid precursor compound in the third stream is lower than the temperature of the plumbing that transports the vapor to a CVD reactor or a plurality of CVD reactors. The flow direction of the first stream, the flow direction of the second stream and the flow direction of the third stream are unidirectional and are not opposed to each other.

This apparatus for manufacturing a laminate comprises: a first sheet transporting device for transporting a first sheet; a water supply device for supplying an aqueous medium to the surface of the first sheet coated with a silane coupling agent and/or the surface of a second sheet coated with a silane coupling agent; and a laminating device for attaching the first sheet and the second sheet which have been supplied with the aqueous medium.

A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a target surface of a first material and a non-target surface of a second material different than the first material is received into the common manufacturing platform. An additive material is deposited on the workpiece with selectivity that results in the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.