A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode and which is in contact with the first electrode. The first electrode includes a first portion including an interface between the first electrode and the dielectric layer, the dielectric layer includes a second portion including the interface, and the first portion and the second portion each contain silicon. A concentration distribution of the silicon along a thickness direction of the first portion and the second portion includes a convex portion intersecting the interface.

The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.

Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.

A method of manufacturing a semiconductor device may include: exposing a surface of a gallium oxide substrate to an acidic or alkaline chemical solution so as to increase a surface roughness of the surface; and forming an electrode on the surface having the increased surface roughness.

Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.

Provided is a method of evaluating a semiconductor substrate, which evaluates quality of the semiconductor substrate by a photoluminescence measurement, wherein the evaluation by the photoluminescence measurement includes, after subjecting a surface of an evaluation-target semiconductor substrate to a pretreatment, irradiating the surface with excitation light, and then detecting emission obtained from the surface having been irradiated with the excitation light, and the pretreatment includes subjecting the surface of the evaluation-target semiconductor substrate to be irradiated with the excitation light to an oxide film formation treatment and charging the surface of the formed oxide film by corona discharge.

Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.

A PERC solar cell capable of improving photoelectric conversion efficiency and a preparation method thereof are provided. The solar cell consecutively includes, from the bottom up, a rear silver electrode (1), a rear aluminum field (2), a rear silicon nitride film (3), a rear aluminum oxide film (4), P-type silicon (5), N-type silicon (6), a front silicon nitride film (7), and a front silver electrode (8). The rear aluminum field (2) is connected to the P-type silicon (5) via a rear aluminum strip (10). The P-type silicon (5) is a silicon wafer of the cell. The N-type silicon (6) is an N-type emitter formed by diffusion via the front surface of the silicon wafer. The front silicon nitride film (7) is deposited on the front surface of the silicon wafer. The rear aluminum oxide film (4) is deposited on the rear surface of the silicon wafer. The rear aluminum oxide film (3) is deposited after the front silicon nitride film (7) is deposited on the silicon wafer, and the rear surface of the silicon wafer is washed before depositing the rear aluminum oxide film (3). The cell can significantly improves passivation effect of the rear aluminum oxide film and improve the open-circuit voltage and short-circuit current of the cell, thereby increasing photoelectric conversion efficiency of the cell.

A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.

Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.