A material suitable for a semiconductor included in a transistor, a diode, or the like is provided. The material is an oxide material including In, M1, M2 and Zn, in which M1 is an element in the group 13 of the periodic table, a typical example thereof is Ga, and M2 is an element whose content is less than the content of M1. Examples of M2 are Ti, Zr, Hf, Ge, Sn, and the like. To contain M2 leads to suppression of generation of oxygen vacancies in the oxide material. A transistor which includes as few oxygen vacancies as possible can be achieved, whereby reliability of a semiconductor device can be increased.

Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

A semiconductor device structure includes a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material. The layer of polycrystalline CVD diamond material is bonded to the layer of single crystal compound semiconductor material via a bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm. The effective thermal boundary resistance as measured by transient thermoreflectance at an interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m.sup.2K/GW with a variation of no more than 12 m.sup.2K/GW as measured across the semiconductor device structure. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm.sup.2V.sup.−1s.sup.−1; and a sheet resistance of no more than 700 Ω/square.

One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

A semiconductor device structure comprising: a layer of compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBR.sub.eff) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m.sup.2K/GW.

An improved method for evaluating GaN wafers. RMS analysis of wafer heights obtained by optical interferometric profilometry is combined with an extreme Studentized deviate (ESD) analysis to obtain a map of the wafer surface that more accurately identifies areas on the surface of a GaN wafer having defects that making those areas unsuitable for fabrication of a vertical electronic device thereon such as bumps and/or pits that can lower the breakdown voltage, increase the on-resistance, and increase the ideality factor.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

Provided is a method of producing a semiconductor epitaxial wafer having enhanced gettering ability. The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions containing carbon, hydrogen, and nitrogen as constituent elements to form a modified layer that is located in a surface portion of the semiconductor wafer and contains the constituent elements of the cluster ions as a solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer.

A method that includes selectively ejecting, from a first nozzle, a patterning material on to a surface of a substrate to define an area within to eject a first printable ammonium-based chalcogenometalate fluid; ejecting, from a second nozzle, the first printable ammonium-based chalcogenometalate fluid within the area defined by the patterning material to form a first layer of the printable ammonium-based chalcogenometalate fluid; and heating the first layer of printable ammonium-based chalcogenometalate fluid to dissipate the first printable ammonium-based chalcogenometalate fluid into a transition metal dichalcogenide having the form MX.sub.2.

Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.