A method of forming a hybrid nanostructure on graphene, the method including providing a graphene layer on a substrate; forming a metal layer on the graphene layer; and chemically depositing a nanomaterial on the graphene layer on which the metal layer is formed to form the hybrid nanostructure.

In a method for electrically doping a semiconducting material, a layer of germanium is formed having a germanium layer thickness, while in situ incorporating phosphorus dopant atoms at a concentration of at least about 510.sup.18 cm.sup.3 through the thickness of the germanium layer during formation of the germanium layer. Additional phosphorus dopant atoms are ex situ incorporated through the thickness of the germanium layer, after formation of the germanium layer, to produce through the germanium layer thickness a total phosphorus dopant concentration of at least about 210.sup.19 cm.sup.3.

Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 m or more. A sheet resistance of a group III-nitride-film-side main surface is 200 /sq or less.

A device comprising a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is disclosed. The device comprises a porous region. The device comprises a first layer disposed between the light emitting layer and the porous region. The device comprises a mask layer disposed between the porous region and the first layer. The device comprises a plurality of openings formed in the mask layer.

Embodiments of the invention are directed to an integrated optogenetic device. The integrated optogenetic includes a substrate layer having a first substrate region and a second substrate region. The device further includes a first contact formed over the substrate layer in the first substrate region and a second contact layer formed over the substrate layer in the second region. In addition, the device includes a light-emitting diode (LED) structure communicatively coupled to the first contact layer and a biosensor element communicatively coupled to the second contact layer. The first contact layer is configured to operate as a bottom contact that provides electrical contact to the LED structure. The first contact layer is further configured to be substantially lattice matched with the substrate layer and a bottom layer of the LED structure.

A template-assisted method for the synthesis of 2D nanosheets comprises growing a 2D material on the surface of a nanoparticle substrate that acts as a template for nanosheet growth. The 2D nanosheets may then be released from the template surface, e.g. via chemical intercalation and exfoliation, purified, and the templates may be reused.

A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.

A vapor phase growth rate measuring apparatus has an initial parameter setting adjuster to set initial values of fitting parameters, a refractive index of each thin film to be formed on the substrate, a growth rate of each thin film, and at least one parameter having temperature dependence, a film thickness calculator to calculate a film thickness of each thin film, a parameter selector to select a value in accordance with a growth temperature for the parameter, a reflectometer to measure a reflectance of the substrate, a reflectance calculator to calculate a reflectance of the substrate, an error calculator to calculate an error between the calculated reflectance and an actual measurement value of the reflectance measured at a plurality of times, a parameter changer to change at least a part of the values of the fitting parameters, and an output value generator to generate characteristic values of each thin film.

Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 m or more. A sheet resistance of a group III-nitride-film-side main surface is 200 /sq or less.

Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.