A silicon carbide epitaxial substrate according to a present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer disposed on the silicon carbide substrate. The silicon carbide epitaxial layer includes a boundary surface in contact with the silicon carbide substrate and a main surface opposite to the boundary surface. The main surface has an outer circumferential edge, an outer circumferential region extending within 5 mm from the outer circumferential edge, and a central region surrounded by the outer circumferential region. When an area density of double Shockley stacking faults in the outer circumferential region is defined as a first area density, and an area density of double Shockley stacking faults in the central region is defined as a second area density, the first area density is five or more times as large as the second area density, the second area density is 0.2 cm.sup.−2 or more.

A semiconductor silicon wafer manufacturing method is provided, where P aggregate defects and SF in an epitaxial layer can be suppressed. A silicon wafer substrate cut from a monocrystal ingot is doped with phosphorus and has a resistivity of 1.05 mΩ.Math.cm or less and a concentration of solid-solution oxygen of 0.9×10.sup.18 atoms/cm.sup.3. The method includes steps of mirror-polishing substrates and heat treatment, where after the mirror-polishing step, the substrate is kept at a temperature from 700° C. to 850° for 30 to 120 minutes, then after the temperature rise, kept at a temperature from 100° C. to 1250° for 30 to 120 minutes, and after cooling, kept at a temperature from 700° C. to 450° C. for less than 10 minutes as an experience time. The heat treatment step is performed in a mixture gas of hydrogen and argon. The method includes an epitaxial layer deposition step to a thickness of 1.3 μm to 10.0 μm.

A nitride semiconductor structure includes a Group III nitride semiconductor portion and a Group II-IV nitride semiconductor portion. The Group III nitride semiconductor portion is single crystalline. The Group III nitride semiconductor portion has a predetermined crystallographic plane. The Group II-IV nitride semiconductor portion is provided on the predetermined crystallographic plane of the Group III nitride semiconductor portion. The Group II-IV nitride semiconductor portion is single crystalline. The Group II-IV nitride semiconductor portion contains a Group II element and a Group IV element. The Group II-IV nitride semiconductor portion forms a heterojunction with the Group III nitride semiconductor portion. The predetermined crystallographic plane is a crystallographic plane other than a (0001) plane.

A wiring substrate includes an insulating substrate including a first surface and a wiring conductor located at the insulating substrate, the insulating substrate containing multiple bulk crystallites of SiC with different polytypes. An electronic device includes the wiring substrate described above and an electronic component mounted on the wiring substrate. An electronic module includes the electronic device described above and a module substrate on which the electronic device is mounted.

A semiconductor device includes: a semiconductor film including a Schottky junction region and an Ohmic junction region; a Schottky electrode arranged on the Schottky junction region; and an Ohmic electrode arranged on the Ohmic junction region, the Schottky junction region having a first dislocation density, the Ohmic junction region having a second dislocation region, and the first dislocation density being smaller than the second dislocation density.

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Provided is a susceptor which makes it possible to increase the circumferential flatness uniformity of an epitaxial layer of an epitaxial silicon wafer. A susceptor 100 is provided with a concave counterbore portion on which a silicon wafer W is placed, and the radial distance L between the center of the susceptor and an opening edge of the counterbore portion varies at 90° periods in the circumferential direction. Meanwhile, when the angle at which the radial distance L is minimum is 0°, the radial distance L is a minimum value L.sub.1 at 90°, 180°, and 270°; and the radial distance L is a maximum value L.sub.2 at 45°, 135°, 225°, and 315°. Accordingly, the pocket width L.sub.p also varies in conformance with the variations of the radial distance L. The opening edge 110C describes four elliptical arcs being convex radially outward when the susceptor 100 is viewed from above.

The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.

The present invention addresses the issue of providing: an SiC substrate having a dislocation conversion layer that can reduce resistance; and a novel technology pertaining to SiC semiconductors. This SiC substrate and SiC semiconductor device comprise a dislocation conversion layer 12 having a doping concentration of at least 1×10.sup.15 cm.sup.−3. As a result of comprising a dislocation conversion layer 12 having this kind of doping concentration: expansion of basal plane dislocations and the occurrence of high-resistance stacking faults can be suppressed; and resistance when SiC semiconductor devices are produced can be reduced.

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.