H01L21/02439

Rare Earth Pnictides for Strain Management
20170353002 · 2017-12-07 ·

Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

A method of fabricating a semiconductor device is described. A first material layer is formed, wherein the first material layer contains crystalline aluminum nitride or aluminum scandium nitride (AlScN) with a first Sc content. A second material layer is formed on the first material layer, wherein the second material layer contains aluminum scandium nitride (AlScN) with a second Sc content higher than the first Sc content. A third material layer is formed on the second material layer, wherein the third material layer contains aluminum scandium (AlSc).

Photonic devices

Photonic devices having Al.sub.1-xSc.sub.xN and Al.sub.yGa.sub.1-yN materials, where Al is Aluminum, Sc is Scandium, Ga is Gallium, and N is Nitrogen and where 0<x≤0.45 and 0≤y≤1.

MAXIMIZING CUBIC PHASE GROUP III-NITRIDE ON PATTERNED SILICON
20170310076 · 2017-10-26 ·

A device including a non-polarization material includes a number of layers. A first layer of silicon (100) defines a U-shaped groove having a bottom portion (100) and silicon sidewalls (111) at an angle to the bottom portion (100). A second layer of a patterned dielectric on top of the silicon (100) defines vertical sidewalls of the U-shaped groove. A third layer of a buffer covers the first layer and the second layer. A fourth layer of gallium nitride is deposited on the buffer within the U-shaped groove, the fourth layer including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111), wherein a deposition thickness (h) of the gallium nitride above the first layer of silicon (100) is such that the c-GaN completely covers the h-GaN between the vertical sidewalls.

MANUFACTURING METHOD OF GALLIUM OXIDE THIN FILM FOR POWER SEMICONDUCTOR USING DOPANT ACTIVATION TECHNOLOGY
20220051892 · 2022-02-17 ·

Disclosed is a method of manufacturing a gallium oxide thin film for a power semiconductor using a dopant activation technology that maximizes dopant activation effect and rearrangement effect of lattice in a grown epitaxial at the same time by performing in-situ annealing in a growth condition of a nitrogen atmosphere at the same time as the growth of a doped layer is finished.

Method of growing nitride semiconductor layer

A method of growing a nitride semiconductor layer may include preparing a substrate in a reactor, growing a first nitride semiconductor on the substrate at a first temperature, the first nitride semiconductor having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate, and removing the substrate at a second temperature.

ELECTRONIC DEVICE, STACKED STRUCTURE, AND MANUFACTURING METHOD OF THE SAME
20170229583 · 2017-08-10 · ·

A stacked structure includes: an insulating substrate; a graphene film that is formed on the insulating substrate; and a protective film that is formed on the graphene film and is made of a transition metal oxide, which is, for example, Cr.sub.2O.sub.3. Thereby, at the time of transfer of the graphene, polymeric materials such as a resist are prevented from directly coming into contact with the graphene and nonessential carrier doping on the graphene caused by a polymeric residue of the resist is suppressed.

ALUMINA SUBSTRATE

An alumina substrate having a carbon-containing phase with an AlN layer formed on a surface of the alumina substrate.

Methods of growing heteroepitaxial single crystal or large grained semiconductor films and devices thereon
09722130 · 2017-08-01 · ·

A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.

Nanowire sized opto-electronic structure and method for modifying selected portions of same
09722135 · 2017-08-01 · ·

A LED structure includes a support and a plurality of nanowires located on the support, where each nanowire includes a tip and a sidewall. A method of making the LED structure includes reducing or eliminating the conductivity of the tips of the nanowires compared to the conductivity of the sidewalls during or after creation of the nanowires.