A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide.

A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is placed on the epitaxial growth surface. A buffer layer is formed on the epitaxial growth surface. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are separated to form a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface.

A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.

Provided is a method for manufacturing a group III nitride semiconductor substrate includes a substrate preparation step S10 of preparing a sapphire substrate, a heat treatment step S20 of performing a heat treatment on the sapphire substrate, a pre-flow step S30 of supplying a metal-containing gas over the sapphire substrate, a buffer layer forming step S40 of forming a buffer layer over the sapphire substrate under growth conditions of a growth temperature of 800° C. or higher and 950° C. or lower and a pressure of 30 torr or more and 200 torr or less, and a growth step S50 of forming a group III nitride semiconductor layer over the buffer layer under growth conditions of a growth temperature of 800° C. or higher and 1025° C. or lower, a pressure of 30 torr or more and 200 torr or less, and a growth speed of 10 μm/h or more.

First, in a first step, a semiconductor layer that is constituted by a nitride semiconductor and includes a group V polar surface as a main surface is formed. Next, in a second step, nitrogen atoms at the surface of the semiconductor layer are substituted with a group VI element that is any of oxygen, sulfur, selenium, and tellurium. Next, in a third step, a layered material layer is formed through epitaxial growth of a layered material on the semiconductor layer at which nitrogen atoms are substituted with the group VI element.

A method of growing patterns of an atomic layer of metal dichalcogenides, the method including providing a substrate, providing aligned patterns of carbon nanostructures on the substrate, providing a first metal portion in contact with a first portion of the patterns of carbon nanostructures and a second metal portion in contact with a second portion of the patterns of carbon nanostructures, depositing a salt layer on the substrate and the patterns of carbon nanostructures, resistively heating the patterns of carbon nanostructures to remove the patterns of carbon nanostructures and salt deposited thereon from the substrate, wherein removing the patterns of carbon nanostructures and salt deposited thereon from the substrate provides salt patterns on the substrate, and growing an atomic layer of metal dichalcogenides on the salt patterns, wherein the atomic layer of metal dichalcogenides is provided in aligned patterns each having a pre-defined width. Also disclosed are patterns of an atomic layer of metal dichalcogenides prepared according to the method of the disclosure.

The present disclosure provides a method and structure for producing large area gallium and nitrogen engineered substrate members configured for the epitaxial growth of layer structures suitable for the fabrication of high performance semiconductor devices. In a specific embodiment the engineered substrates are used to manufacture gallium and nitrogen containing devices based on an epitaxial transfer process wherein as-grown epitaxial layers are transferred from the engineered substrate to a carrier wafer for processing. In a preferred embodiment, the gallium and nitrogen containing devices are laser diode devices operating in the 390 nm to 425 nm range, the 425 nm to 485 nm range, the 485 nm to 550 nm range, or greater than 550 nm.

Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.