Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.

The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.

A C-plane GaN substrate only mildly restricts the shape and dimension of a nitride semiconductor device formed on the substrate. The variation of an off-angle on the main surface of the substrate is suppressed. In the C-plane GaN substrate: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on the main surface; the number density of the facet growth area accompanied by a core among the plurality of facet growth areas is less than 5 cm.sup.−2 on the main surface; and, when any circular area of 4 cm diameter is selected from an area which is on the main surface and is distant by 5 mm or more from the outer peripheral edge of the substrate, the variation widths of an a-axis direction component and an m-axis direction component of an off-angle within the circular area is each 0.25 degrees or less.

A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.

The electronic device comprises a substrate (1), at least one semiconductor wire element (2) formed by a nitride of a group III material and an electroconductive layer (3) interposed between the substrate (1) and said at least one semiconductor wire element (2). Said at least one semiconductor wire element (2) extends from said electroconductive layer (3), and the electroconductive layer (3) comprises a carbide of zirconium or a carbide of hafnium.

The present disclosure provides a fabrication of M-plane gallium nitride which is able to grow M-plane gallium nitride without the need of expensive substrates, such as LiAlO.sub.2, LiGaO.sub.2 or SiC. The fabrication of M-plane gallium nitride includes preparing a zinc oxide hexagonal prism having a growth face, and growing a gallium nitride layer on the growth face of the zinc oxide hexagonal prism. The growth face is an M-plane perpendicular to a direction of gravity.

A substrate with a (001) orientation is provided. A gallium arsenide (GaAs) layer is epitaxially grown on the substrate. The GaAs layer has a reconstruction surface that is a 4×6 reconstruction surface, a 2×4 reconstruction surface, a 3×2 reconstruction surface, a 2×1 reconstruction surface, or a 4×4 reconstruction surface. Via an atomic layer deposition process, a single-crystal structure yttrium oxide (Y.sub.2O.sub.3) layer is formed on the reconstruction surface of the GaAs layer. The atomic layer deposition process includes water or ozone gas as an oxygen source precursor and a cyclopentadienyl-type compound as an yttrium source precursor.

According to one embodiment, a nitride crystal includes first, second, and third nitride crystal regions. The third nitride crystal region includes Al, and is provided between the first and second nitride crystal regions. A third oxygen concentration in the third nitride crystal region is greater than a first oxygen concentration in the first nitride crystal region and greater than a second oxygen concentration in the second nitride crystal region. A third carbon concentration in the third nitride crystal region is greater than a first carbon concentration in the first nitride crystal region and greater than a second carbon concentration in the second nitride crystal region. A <0001> direction of the first nitride crystal region is one of a first orientation from the second nitride crystal region toward the first nitride crystal region or a second orientation from the first nitride crystal region toward the second nitride crystal region.

This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefitting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride.

A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.