A semiconductor composite layer can include a source electrode and a drain electrode individually comprising both a carrier mobility contributor and an amorphous phase stabilizer. The semiconductor composite layer can further include a semiconductive portion disposed between the source electrode and the drain electrode wherein the semiconductive portion comprises the carrier mobility contributor and the amorphous phase stabilizer, the semiconductivity controller comprising oxygen and an element having an electrode potential that is lower than that of both the carrier mobility contributor and the amorphous phase stabilizer.

In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

A substrate for epitaxial growth includes a central region that has a center of the substrate and that serves as a non-modified region, and a peripheral region that surrounds the central region in a manner to be spaced apart from the center of the substrate by a distance and that serves as a modified region having a plurality of modified points. A method for manufacturing a substrate for epitaxial growth includes providing a substrate and forming a plurality of modified points in an interior of the substrate in position corresponding to the modified region. A semiconductor device including the substrate and a method for manufacturing the semiconductor device are also disclosed.

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Printable inks based on a 2D semiconductor, such as MoS2, and its applications in fully inkjet-printed optoelectronic devices are disclosed. Specifically, percolating films of MoS2 nanosheets with superlative electrical conductivity (10-2 s m-1) are achieved by tailoring the ink formulation and curing conditions. Based on an ethyl cellulose dispersant, the MoS2 nanosheet ink also offers exceptional viscosity tunability, colloidal stability, and printability on both rigid and flexible substrates. Two distinct classes of photodetectors are fabricated based on the substrate and post-print curing method. While thermal annealing of printed devices on rigid glass substrates leads to a fast photoresponse of 150 μs, photonically annealed devices on flexible polyimide substrates possess high photoresponsivity exceeding 50 mA/W. The photonically annealed photodetector also significantly reduces the curing time down to the millisecond-scale and maintains functionality over 500 bending cycles, thus providing a direct pathway to roll-to-roll manufacturing of next-generation flexible optoelectronics.

An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.

A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.