An epitaxial silicon wafer includes: a silicon wafer doped with phosphorus as a dopant and having an electrical resistivity of less than 1.0 m Ω.Math.cm; and an epitaxial film formed on the silicon wafer. The silicon wafer includes: a main surface to which a (100) plane is inclined; and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°30′ to 0°55′ in any direction with respect to an axis perpendicular to the main surface. The epitaxial silicon wafer has at most 1/cm.sup.2 of a density of a hillock defect generated thereon.

Disclosed are an epitaxial wafer and a method of fabricating the same, and an electrochemical sensor, wherein the reference electrode comprises: a substrate (11); an InGaN layer (12) formed on a surface of the substrate (11) and having an In content between 20% and 60% so as to ensure that a transition from negatively charged surface states to positively charged surface states occurs within a composition range; and an InN layer (13) formed on a surface of the InGaN layer (12) facing away from the substrate (11) to act as a stabilization layer. The InGaN layer (12) with an In content between 20% and 60% allows generation of an electrochemical response independent of the concentration of a solution to be detected; and in addition, the InN layer (13) with a high density of intrinsic, positively charged surface states further improves the electrochemical stability of the reference electrode.

The inventive method provides for a method of p-type doping of Ga.sub.2O.sub.3 without adding impurity elements. Embodiments allow for significant simplification relative to extrinsic impurity element doping, and thus offers a reduced fabrication cost while being more temperature resistant since the defect dopants require higher temperatures to alter their impact. Certain methods disclosed provide for p-type gallium oxide formation via intrinsic defect doping, without requiring the addition of impurity elements which provide significant simplification relative to the existing state of the art approaches providing more temperature and radiation resistance, while offering a reduced fabrication cost.

A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.

A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

Compounds and method of preparation of Si—X and Ge—X compounds (X=N, P, As and Sb) via dehydrogenative coupling between the corresponding unsubstituted silanes and amines (including ammonia) or phosphines catalyzed by metallic catalysts is described. This new approach is based on the catalytic dehydrogenative coupling of a Si—H and a X—H moiety to form a Si—X containing compound and hydrogen gas (X=N, P, As and Sb). The process can be catalyzed by transition metal heterogenous catalysts such as Ru(O) on carbon, Pd(O) on MgO) as well as transition metal organometallic complexes that act as homogeneous catalysts. The —Si—X products produced by dehydrogenative coupling are inherently halogen free. Said compounds can be useful for the deposition of thin films by chemical vapor deposition or atomic layer deposition of Si—containing films.

A film forming apparatus is disclosed. The apparatus comprises a chamber; an exhaust unit configured to reduce the pressure in the chamber to a predetermined vacuum level; a holder disposed in the chamber and configured to hold a film forming target member on which a film is to be formed; a supply unit configured to supply a film forming material containing silicon to a surface of the film forming target member; and a heat source configured to perform heating at the predetermined vacuum level to melt the supplied film forming material.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

The present disclosure relates to a method and device for decreasing generation of surface oxide of aluminum nitride. In a physical vapor deposition process, the aluminum nitride is deposited on a substrate in a deposition chamber to form an aluminum nitride coated substrate. A cooling chamber and a cooling load lock module respectively perform a first stage cooling and a second stage cooling on the aluminum nitride coated substrate in vacuum environments, so as to prevent the aluminum nitride coated substrate with the high temperature from being exposed in an atmosphere environment to generate the surface oxide. The method and device for decreasing the generation of the surface oxide of the aluminum nitride can further eliminate crystal defects caused by that gallium nitride is deposited on the surface oxide of the aluminum nitride in the next process.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.