Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

A semiconductor device has a first substrate made of a first semiconductor material, such as silicon. A sacrificial layer is formed over a first surface of the first substrate. A seed layer is formed over the sacrificial layer. A compliant layer is formed over a second surface of the first substrate opposite the first surface of the first substrate. A first semiconductor layer made of a second semiconductor material, such as silicon carbide, dissimilar from the first semiconductor material is formed over the sacrificial layer. The first substrate and sacrificial layer are removed leaving the first semiconductor layer substantially defect-free. The first semiconductor layer containing the second semiconductor material is formed at a temperature greater than a melting point of the first semiconductor material. A second semiconductor layer is formed over the first semiconductor layer with an electrical component formed in the second semiconductor layer.

Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.

Exemplary deposition methods may include delivering a silicon-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the inert gas. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The processing region may be maintained free of helium delivery during the deposition method.

An artificial two-dimensional (2D) material includes a layered atomic structure including a middle atomic layer, a lower atomic layer, and an upper atomic layer. The lower and upper atomic layers are disposed on lower and upper surfaces of the middle atomic layer respectively. The middle atomic layer is a 2D planar atomic structure formed of a transition metal. The lower and upper atomic layers are a 2D planar atomic structure formed of heterogeneous atoms. Atoms of the layered atomic structure are bound by chemical bonding.

A method for manufacturing a semiconductor layer is provided. The method for manufacturing a semiconductor layer may include preparing a substrate, and conducting a first unit process of reacting a first precursor including indium (In) and a first reaction source and a second unit process of reacting a second precursor including gallium (Ga) and a second reaction source to form a semiconductor layer including the indium and the gallium on the substrate.

Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon as-deposited may be characterized by less than or about 3% hydrogen incorporation.

A film forming method for forming a silicon film having a step coverage on a substrate having a recess in a surface of the substrate, the film forming method comprising: forming a silicon film such that a film thickness on an upper portion of a side wall of the recess is thicker than a film thickness on a lower portion of the side wall of the recess by supplying a silicon-containing gas to the substrate; and etching a portion of the silicon film conformally by supplying an etching gas to the substrate, wherein the act of forming the silicon film and the act of etching the portion of the silicon film are performed a number of times which is determined depending on the step coverage.

A graphene compound made from the method of preparing graphene flakes or chemical vapor deposition grown graphene films on a SiO.sub.2/Si substrate; exposing the graphene flakes or the chemical vapor deposition grown graphene film to hydrogen plasma; performing hydrogenation of the graphene; wherein the hydrogenated graphene has a majority carrier type; creating a bandgap from the hydrogenation of the graphene; applying an electric field to the hydrogenated graphene; and tuning the bandgap.

A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.