An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

A semiconductor device includes a doped substrate, a barrier layer, a channel layer, and a doped semiconductor structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate and at a position lower than the channel layer, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween.

A semiconductor device includes a doped substrate, a barrier layer, a channel layer, a doped semiconductor structure, and the conductive structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween. The conductive structure is disposed over the doped substrate and makes contact with the doped semiconductor structure, in which the conductive structure extends from the doped semiconductor structure to a position higher than the channel layer and the barrier layer.

A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms.

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

The present invention is related to a substrate (10) for a controlled implantation of ions (80) into a bulk (20), the substrate (10) comprising the bulk (20) composed of a crystalline first material (70), the bulk (20) comprising an implantation region (28) and a surface (22), wherein the implantation region (28) is located within the bulk (20) and along an implantation direction (82) at an implantation depth (26) below an implantation area (24) on the surface (10) of the bulk (20). Further, the present invention is related to a method of preparing a substrate (10) for a controlled implantation of ions (80) into a bulk (20), preferably the aforementioned substrate (10), the substrate (10) comprising the bulk (20) composed of a crystalline first material (70), the bulk (20) comprising an implantation region (28) and the surface (22), wherein the implantation region (28) is located within the bulk (20) and along an implantation direction (82) at an implantation depth (26) below an implantation area (24) on the surface (22) of the bulk (20).

The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively.