A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.

The present invention relates to the field of semiconductors, and discloses a manufacturing method of a super junction and a super-junction Schottky diode thereof. The manufacturing method of the super junction includes forming an epitaxial layer on the surface of a wide-bandgap semiconductor substrate by an epitaxial growth process; implanting first doping ions into at least part of a region of the epitaxial layer along a preset crystal orientation of the wide-bandgap semiconductor to form a first conductive type region; and implanting second doping ions into at least part of the first conductive type region along the preset crystal orientation of the wide-bandgap semiconductor to form a second conductive type region, wherein the second doping ions and the first doping ions have different conductive types, and the preset crystal orientation is a crystal orientation which enables the doping ions to generate a channel effect when the doping ions are implanted along the preset crystal orientation.

First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

A semiconductor device has a cell region formed with a semiconductor element and an outer peripheral region surrounding the cell region. The outer peripheral region includes a guard ring part having a plurality of guard rings of the second conductivity-type, and a plurality of guard ring column regions of the second conductivity-type. Each of the guard rings is disposed in a surface layer portion of the drift layer and has a frame shape surrounding the cell region. The guard ring column regions are extended from the guard rings toward the substrate. Each of the guard ring column regions has a width smaller than a width of each of the guard rings in a direction along a planar direction of the substrate in a predetermined cross-section defined along the cell region and the outer peripheral region. At least two guard ring column regions are provided for each guard ring.

A method for thermally processing a substrate having a surface region and a buried region with a pulsed light beam, the substrate presenting an initial temperature-depth profile and the surface region presenting an initial surface temperature, including steps of: illuminating the surface region with a preliminary pulse so that it generates an amount of heat and reaches a predetermined preliminary surface temperature; and illuminating the surface region with a subsequent pulse after a time interval so that it reaches a predetermined subsequent surface temperature. The time interval is determined such that the surface region reaches a predetermined intermediate surface temperature greater than the initial surface temperature, such that during the time interval, the amount of heat is diffused within the substrate down to a predetermined depth so that the substrate presents a predetermined intermediate temperature-depth profile.

A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

A silicon carbide device includes: a planar gate structure on a first surface of a silicon carbide substrate, the planar gate structure having a gate length along a lateral first direction; a source region of a first conductivity type extending under the planar gate structure over at least part of the gate length; a body region of a second conductivity type, the body region including a channel zone that adjoins the source region under the planar gate structure; and a shielding region of the second conductivity type covering the channel zone over at least 20% but less than 100% of the gate length, wherein a maximum dopant concentration in the shielding region is higher than a maximum dopant concentration in the body region.

A method of manufacturing a silicon carbide semiconductor device includes selectively forming a semiconductor region of a conductivity type at a first main surface of a semiconductor substrate containing silicon carbide; forming a nickel layer above the semiconductor region; ion-implanting aluminum in the nickel layer; performing a heat treatment to the nickel layer implanted with the aluminum to thereby form an ohmic contact layer in ohmic contact with the semiconductor region; forming a first electrode that is in contact with the ohmic contact layer, the semiconductor region, and the semiconductor substrate; and forming a second electrode on a second main surface of the semiconductor substrate.

A base layer has a low concentration peak at a position between a portion located at a same depth as a lower end portion of a gate electrode and a portion located at a same depth as an upper end portion of the gate electrode in a concentration profile of an impurity concentration in a depth direction. An impurity region has a boundary with the base layer in the depth direction at a position between a first peak position, at which the impurity concentration of the base layer is maximum between the portion located at the same depth as the lower end portion and the position of the low concentration peak, and a second peak position, at which the impurity concentration of the base layer is maximum between the position of the low concentration peak and the portion located at the same depth as the upper end portion.