A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.

A SiC ohmic contact preparation method is provided and includes: selecting a SiC substrate; preparing a graphene/SiC structure by forming a graphene on a Si-face of the SiC substrate; depositing an Au film on the graphene of the graphene/SiC structure; forming a first transfer electrode pattern on the Au film by a first photolithography; etching the Au film uncovered by the first transfer electrode pattern through a wet etching; etching the graphene uncovered by the Au film through a plasma etching after the wet etching; forming a second transfer electrode pattern on the SiC substrate by a second photolithography; depositing an Au material on the Au film exposed by the second transfer electrode pattern and forming an Au electrode and then annealing. The graphene reduces potential barrier associated with the SiC interface, specific contact resistance of ohmic contact reaches the order of 10.sup.−7˜10.sup.−8 Ω.Math.cm.sup.2, and the method has high repeatability.

A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode.

Systems and methods are presented herein that facilitate temporally synchronizing, in real time, a separately sourced high quality audio segment of a live event with a video segment that is generated by a recording device associated with a member of the audience. An A-V Synchronization Application may synchronize a video segment of a live event that is generated from a personal electronic device of an audience member with a high quality audio segment that is separately sourced and generated by professional sound recording equipment at the live event. The result of the temporal synchronization is a high fidelity digital audio visual recording of the live event. In various, the audience member may stream, in real-time, the high fidelity digital audio visual recording to an additional electronic device at a different geo-location. In some examples, narrative audio segments may be also included as part of the high fidelity digital audio visual recording.

A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

A method for forming a semiconductor device includes implanting first ions and second ions into a p-type silicon carbide layer from a first main side to form an implantation layer at the first main side. The implanting is performed by plasma immersion ion implantation in which the p-type silicon carbide layer is immersed in a plasma comprising the first ions and the second ions. The first ions can be ionized aluminum atoms and the second ions are different from the first ions.

A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, an Al-based oxide film interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.

A method of manufacturing a semiconductor device includes assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate where the epitaxial-growth layer is grown on a bulk layer and forming a plurality of device structures on the plurality of chip regions, respectively, thinning the semiconductor substrate from a bottom-surface side of the bulk layer, bonding a supporting-substrate on a bottom surface of the thinned semiconductor substrate, selectively removing the supporting-substrate so that the bottom surface of the semiconductor substrate is exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively, dicing the semiconductor substrate together with the supporting-substrate along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.

A method for manufacturing a wide bandgap junction harrier Schottky diode (1) having an anode side (10) and a cathode side (15) is provided, wherein an (n±) doped cathode layer (2) is arranged on the cathode side (15), at least one p doped anode layer (3) is arranged on the anode side (10), an (n−) doped drift layer (4) is arranged between the cathode layer (2) and the at least one anode layer (3), which drift layer (4) extends to the anode side (10), wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate(100), b) creating the drift layer (4) on the cathode layer (2), c) creating the at least one anode layer (3) on the drift layer (4), d) applying a first metal layer (5) on the anode side (10) on top of the drift layer (4) for forming a Schottky contact (55), characterized in, that e) creating a second metal layer (6) on top of at least one anode layer (3), wherein after having created the first and the second metal layer (5, 6), a metal layer on top of the at least one anode layer (3) has a second thickness (64) and a metal layer on top of the drift layer (4) has a first thickness (54), wherein the second thickness (64) is smaller than the first thickness (54), 1) then performing a first heating step (63) at a first temperature, by which due the second thickness (64) being smaller than the first thickness (54) an ohmic contact (65) is formed at the interface between the second metal layer (6) and the at least one anode layer (3), wherein performing the first healing step (63) such that a temperature below the first metal layer (5) is kept below a temperature for forming an ohmic contact.

After a titanium nitride film is formed to cover an interlayer insulating film, a first nickel film is formed on a front surface of a silicon carbide base exposed in a contact hole, so as to extend on the titanium nitride film. Next, the silicon carbide base and the first nickel film are reacted by rapid thermal annealing at a temperature of 800 to 1100 degrees C. to form a nickel silicide film that forms an ohmic contact. Grains of the titanium nitride film are enlarged by the rapid thermal annealing, making a grain size of the titanium nitride film 20 nm to 50 nm. Thus, interstices of the grains of the titanium nitride film become smaller than before the rapid thermal annealing or are eliminated, enabling the intrusion of nickel from the first nickel film into the interstices of the columnar grains of the titanium nitride film to be suppressed.