The object of a silicon carbide semiconductor device according to the present disclosure is to prevent fluctuations in threshold voltage and prevent cracks in a barrier metal. A silicon carbide semiconductor device includes: a silicon carbide substrate; a semiconductor layer formed on the silicon carbide substrate; a gate electrode facing the semiconductor layer through a gate insulating film; an interlayer insulating film covering the gate electrode; a barrier metal formed on the interlayer insulating film; and a top electrode covering the barrier metal, wherein the barrier metal has a two-layer structure of a barrier metal and a barrier metal, and the barrier metal closer to the interlayer insulating film is made of a same metallic material as the barrier metal, the barrier metal being thinner than the barrier metal.

A method of manufacturing a semiconductor device includes forming a trench that extends from a first surface into a silicon carbide body. A first doped region and an oppositely doped second doped region are formed in the silicon carbide body. A lower layer structure is formed on a lower sidewall portion of the trench. An upper layer stack is formed on an upper sidewall portion and/or on the first surface. The first doped region and the upper layer stack are in direct contact along the upper sidewall portion and/or on the first surface. The second doped region and the lower layer structure are in direct contact along the lower sidewall portion.

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

A wide gap semiconductor device has a wide gap semiconductor layer 10; and a metal electrode 20 disposed on the wide gap semiconductor layer 10. The metal electrode 20 has a monocrystalline layer 21 having a hexagonal close-packed (HCP) structure in an interface region between the metal electrode 20 and the wide gap semiconductor layer 10. The monocrystalline layer 21 has a specific element-containing region 22 containing O, S, P or Se.

Provided is a method for manufacturing a semiconductor device, the method including: performing first ion implantation ion-implanting a p-type impurity into a silicon carbide layer; performing second ion implantation ion-implanting carbon (C) into the silicon carbide layer; performing a first heat treatment activating the p-type impurity; performing a first oxidation treatment oxidizing the silicon carbide layer; performing an etching treatment etching the silicon carbide layer in an atmosphere containing hydrogen gas; forming a first metal film containing at least one metal element selected from the group consisting of nickel, palladium, platinum, and chromium; performing a second heat treatment causing the silicon carbide layer to react with the first metal film to form a metal silicide layer containing the at least one metal element; and forming a second metal film having a chemical composition different from a chemical composition of the first metal film.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face; a trench in the silicon carbide layer extending in a first direction; a gate electrode disposed in the trench; a first silicon carbide region of n-type; a second silicon carbide region of p-type between the first silicon carbide region and the first face being shallower than the trench; a third silicon carbide region of n-type disposed between the second silicon carbide region and the first face; a fourth silicon carbide region of n-type disposed between the third silicon carbide region and the first face, a width of the fourth silicon carbide region in a second direction perpendicular to the first direction being smaller than a width of the third silicon carbide region in the second direction; and a first electrode in contact with the fourth silicon carbide region.

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate having a front surface and a rear surface, and an ohmic electrode in ohmic contact with silicon carbide of at least one of the front surface or the rear surface of the silicon carbide semiconductor substrate. The ohmic electrode is made of Ni containing 0.1 wt % or more and 15 wt % or less of P as an impurity. The ohmic electrode contains Ni silicide including NiSi. The ohmic electrode further contains Ni.sub.5P.sub.2 in the Ni silicide. A method for manufacturing the silicon carbide semiconductor device includes forming a metal thin film on the silicon carbide that is to be in ohmic contact with the ohmic electrode, and forming the ohmic electrode by laser annealing that includes irradiating the metal thin film with laser light and reacting the Ni with Si in the silicon carbide to generate Ni silicide.

Method for manufacturing an electronic device, comprising the steps of: forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 5*10.sup.2/cm.sup.2; attaching an acceptor layer at the graphene layer to form a wafer-stack, the acceptor layer comprising silicon carbide having a second defect density higher than the first defect density; forming an epitaxial silicon carbide layer; splitting the wafer-stack along a split plane in the silicon carbide substrate to form a device wafer comprising the graphene layer and a silicon carbide split layer at the graphene layer; and further processing the device wafer at the upper side.

An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N− drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.