Patent classifications
H01L21/2003
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
A cavity structure comprises one or more seed surfaces, a first growth path for the growth of a first semiconductor structure from one of the one or more seed surfaces and a second growth path for the growth of a second semiconductor structure from one of the one or more seed surfaces. The cavity structure further comprises at least one opening for supplying precursor materials to the cavity structure. A method can include selectively growing the first semiconductor structure along the first growth path and selectively growing the second semiconductor structure along the second growth path. The first semiconductor structure has a first growth front and the second semiconductor structure has a second growth front. The method can further include merging the first and the second growth front at a border area of the first and the second semiconductor structure.
SENSE AMPLIFIER LAYOUT FOR FINFET TECHNOLOGY
A sense amplifier (SA) includes a semiconductor substrate having a source/drain (S/D) diffusion region; a pair of SA sensing devices both disposed in the S/D diffusion region; an SA enabling device disposed in the same S/D diffusion region as where the pair of SA sensing devices are disposed in; and a sense amplifier enabling signal (SAE) line for carrying an SAE signal, for turning on the SA enabling device to discharge one of the pair of SA sensing devices during a data read from the sense amplifier, wherein the SA enabling device is arranged to provide buffer protection for source/drain terminals of the pair of SA sensing devices.
GaN laminate and method of manufacturing the same
To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.
Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
On a front surface of an n.sup.+-type starting substrate containing silicon carbide, a pin diode is configured having silicon carbide layers constituting an n.sup.+-type buffer layer, an n.sup.-type drift layer, and a p.sup.+-type anode layer sequentially formed by epitaxial growth. The n.sup.+-type buffer layer is formed by so-called co-doping of nitrogen and vanadium, which forms a recombination center, together with an n-type impurity. The n.sup.+-type buffer layer includes a first part disposed at a side of a second interface of the buffer layer with the substrate and a second part disposed at side of a first interface of the buffer layer with the drift layer. The vanadium concentration in the second part is lower than that in the first part. The vanadium concentration in the second part is at most one tenth of the maximum value Vmax of the vanadium concentration in the n.sup.+-type buffer layer.
GaN material and method of manufacturing semiconductor device
There is provided a new technology for anodic oxidation etching performed to GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of 1 V while irradiating the GaN material with UV light to form the recess of 2 m in depth.
Sense amplifier layout for FinFET technology
A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.
Mirror plate for a fabry-perot interferometer and a fabry-perot interferometer
A method for producing a mirror plate for a Fabry-Perot interferometer includes providing a substrate, which includes silicon, implementing a semi-transparent reflective coating on the substrate, forming a passivated region in and/or on the substrate by etching a plurality of voids in the substrate, and by passivating the surfaces of the voids, forming a first sensor electrode on top of the passivated region, and forming a second sensor electrode supported by the substrate.
LASER PROCESSING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND AMORPHOUS SILICON CRYSTALLIZATION METHOD
A laser processing apparatus includes: a laser light source that generates a laser beam; a first beam splitter on which the laser beam is incident; a second beam splitter on which the laser beam having passed through the first beam splitter is incident; and a homogenizer that controls an energy density of the laser beam emitted from the second beam splitter. The laser beam output from the homogenizer includes a p-polarized component and an s-polarized component, and a ratio of energy intensity of the p-polarized component to the s-polarized component is preferably not lower than 0.74 and not higher than 1.23 on a surface of the workpiece.
GaN MATERIAL AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
There is provided a new technology for anodic oxidation etching performed to GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of 1 V while irradiating the GaN material with UV light to form the recess of 2 m in depth.
GaN LAMINATE AND METHOD OF MANUFACTURING THE SAME
To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.