Protons are injected from a back surface side of a semiconductor substrate to repair both defects within the semiconductor substrate and also defects in a channel forming region on a front surface side of the semiconductor substrate. As a result, variation in gate threshold voltage is reduced and leak current when a reverse voltage is applied is reduced. Provided is a semiconductor device including a semiconductor substrate that includes an n-type impurity region containing protons, on a back surface side thereof; and a barrier metal that has an effect of shielding from protons, on a front surface side of the semiconductor substrate.

A system and method of patterning dopants of opposite polarity to form a solar cell is described. Two dopant films are deposited on a substrate. A laser is used to pattern the N-type dopant, by mixing the two dopant films into a single film with an exposure to the laser and/or drive the N-type dopant into the substrate to form an N-type emitter. A thermal process drives the P-type dopant from the P-type dopant film to form P-type emitters and further drives the N-type dopant from the single film to either form or further drive the N-type emitter.

A structure includes a dopant layer at or close to a channel to n-dope TMDs, wherein the dopant layer includes at least one of: at least one of halides (MX.sub.2; M=(Ti, Zr, or Hf), X=at least one of {Cl, Br, or I}); at least one of hydroxides (M(OH).sub.2; M=(Ru, Os, or Ni)); Ca.sub.4As.sub.4; or Zn.sub.2H.sub.8N.sub.4Te.sub.2. A method for fabricating a channel includes depositing a delta-doped layer having a low dielectric constant and a band gap>0.1 eV onto a high-k layer, and n-doping a TMD layer, wherein an absolute value of ionization energy of the delta-doped layer is less than an absolute value of the electron affinity of the TMD layer, the delta-doped layer includes one of a halide, hydroxide, chalcogenide, oxide, arsenide, or multi-anion compound, and a fractional ratio of the delta-doped layer to the high-k layer is 0 to 0.3.

According to some embodiments of the present disclosure, methods of forming a semiconductor device on a semiconductor layer having opposing first and second surfaces are disclosed. An n-type doped region including an n-type dopant may be formed at the first surface of the semiconductor layer. A p-type dopant source layer including a p-type dopant may be formed on the n-type doped region. The p-type dopant may be diffused from the p-type dopant source layer through the n-type doped region into the semiconductor layer to form a p-type doped region of the semiconductor layer, and the p-type doped region of the semiconductor layer may be between the n-type doped region and the second surface of the semiconductor layer. After diffusing the p-type dopant, the p-type dopant source layer may be removed.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600 C. (e.g., about 300 C. to about 500 C.). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high- k/interfacial interface 0.5 nm.