A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath.

A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.

A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.

The present invention provides a boron diffusion layer forming method capable of sufficiently oxidizing a boron silicide layer formed on a silicon substrate to remove it and obtaining a high-quality boron silicate glass layer. The present invention is a boron diffusion layer forming method of forming a boron diffusion layer on a silicon substrate by a boron diffusion process, the process including a first step of thermally diffusing boron on the silicon substrate and a second step of oxidizing a boron silicide layer formed on the silicon substrate at the first step, wherein the second step has a state at a temperature of 900° C. or higher and a treatment temperature at the first step or lower, for 15 minutes or more.

The present invention provides a boron diffusion layer forming method capable of sufficiently oxidizing a boron silicide layer formed on a silicon substrate to remove it and obtaining a high-quality boron silicate glass layer. The present invention is a boron diffusion layer forming method of forming a boron diffusion layer on a silicon substrate by a boron diffusion process, the process including a first step of thermally diffusing boron on the silicon substrate and a second step of oxidizing a boron silicide layer formed on the silicon substrate at the first step, wherein the second step has a state at a temperature of 900° C. or higher and a treatment temperature at the first step or lower, for 15 minutes or more.

A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.

Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.