A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*10.sup.14 cm.sup.−3 at least in a first portion of the silicon semiconductor body, the first portion extending from the main surface to a depth of about 50 μm. The nitrogen concentration increases with a distance from the main surface at least in the first portion. The semiconductor device further includes a field-effect structure arranged next to the main surface.

A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*10.sup.14 cm.sup.−3 at least in a first portion of the silicon semiconductor body, the first portion extending from the main surface to a depth of about 50 μm. The nitrogen concentration increases with a distance from the main surface at least in the first portion. The semiconductor device further includes a field-effect structure arranged next to the main surface.

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.

A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.

An ion implantation system having a grid assembly. The system includes a plasma source configured to provide plasma in a plasma region; a first grid plate having a plurality of apertures configured to allow ions from the plasma region to pass therethrough, wherein the first grid plate is configured to be biased by a power supply; a second grid plate having a plurality of apertures configured to allow the ions to pass therethrough subsequent to the ions passing through the first grid plate, wherein the second grid plate is configured to be biased by a power supply; and a substrate holder configured to support a substrate in a position where the substrate is implanted with the ions subsequent to the ions passing through the second grid plate.

The present disclosure relates to roll-to-roll doping method of graphene film, and doped graphene film.

The present disclosure relates to roll-to-roll doping method of graphene film, and doped graphene film.

Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.