A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

A method of fabricating a laterally diffused metal oxide semiconductor transistor including providing a substrate, forming a first well of a first doping polarity type in the substrate, forming a gate on a portion of the first well, the gate including an oxide layer and an at least partially conductive layer on the oxide layer, and forming a mask on at least a portion of the gate and at least a portion of the first well, wherein the mask has a sloping edge. The method further includes forming a second well of a second doping polarity type at least partially in the first well by implanting ions in the first well, the second well extending under a portion of the gate, the second doping polarity type being of opposite type to the first doping polarity type. The method includes forming a first one of a source and drain of the first doping polarity type in or on the second well, thereby defining a channel of the transistor under the gate. The method further includes forming a second one of the source and drain of the first doping polarity type in or on the first well, wherein the implanting includes directing at least a first beam of ions towards the first well at an angle substantially perpendicular to a surface plane of the substrate, and directing at least a second beam of ions towards the first well at an angle substantially offset from a surface normal of the substrate.

A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.

A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.

A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.