A method of forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device includes: providing a semiconductor body; implanting a dopant to form a doped region in the semiconductor body; providing, above the doped region, a mask layer having a first section and a second section, the first section having has a first thickness along a vertical direction and the second section having a second thickness along the vertical direction, the second thickness being different from the first thickness; and subjecting the doped region and both mask sections to a laser thermal annealing, LTA, processing step.

A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.

Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The method includes: forming a first material layer and a second material layer sequentially on a substrate; defining an active region of the semiconductor device on the substrate, the first material layer and the second material layer, wherein the active region includes a channel region; forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer; forming a first source/drain region and a second source/drain region on the substrate and the second material layer respectively; and forming a gate stack around the outer periphery of the channel region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region.

An embodiment of the present the disclosure provides a memory device, including: a substrate, an interconnection structure disposed on the substrate, a conductive layer disposed on the interconnection structure, a stop layer disposed on the conductive layer, and a gate stack structure disposed on the stop layer. The gate stack structure includes a plurality of insulating layers and a plurality of gate conductive layers that alternate with each other. A ratio of a thickness of a bottommost insulating layer of the gate stack structure to a thickness of the stop layer is 1:1 to 1:2. The memory device further includes a channel pillar extending through the gate stack structure and the stop layer and to electrically connect the conductive layer, and a charge storage structure disposed between sidewalls of the channel pillar and the plurality of gate conductive layers.

This application discloses an NMOS device and an integrated circuit. The NMOS device includes a semiconductor substrate, a gate oxide layer, and a gate. The semiconductor substrate includes a P well, a source region, a drain region, a first LDD region, and a second LDD region. The first LDD region and the second LDD region each include a first ion injection region and a second ion injection region. The first ion injection region is formed by injecting a first ion, and the first ion includes a P ion. The second ion injection region is formed by injecting a second ion into the first ion injection region, and the second ion includes a Ge ion.