Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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H01L21/02
Manufacture or treatment of semiconductor devices or of parts thereof
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the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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H01L21/18
the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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H01L21/24
Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
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H01L21/244
Alloying of electrode materials
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H01L21/244

III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology
20170040219 · 2017-02-09 ·

In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.