The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.

A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region forms a semiconductor fin.

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; fins on the semiconductor substrate; an isolation layer formed on the semiconductor substrate and between adjacent fins; and gate structures on sides of the isolation layer. The isolation layer has a top surface higher than top surfaces of the fins and passes through the fins along a direction perpendicular to an extending direction of the fins and in parallel with a surface of the semiconductor substrate.

A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; and a control electrode between the semiconductor part and the second electrode. The control electrode is provided inside a trench of the semiconductor part. The control electrode is electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the second electrode by a second insulating film. The control electrode includes an insulator at a position apart from the first insulating film and the second insulating film. The semiconductor part includes a first layer of a first conductivity type provided between the first and second electrodes, the second layer of a second conductivity type provided between the first layer and the second electrode and the third layer of the first conductivity type selectively provided between the second layer and the second electrode.

A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.

A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a metal gate stack over the semiconductor substrate. The semiconductor device structure also includes a spacer element over a sidewall of the metal gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. An atomic concentration of the dopant decreases along a direction from an inner surface of the spacer element adjacent to the metal gate stack towards an outer surface of the spacer element.

An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.